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	DCW	-3
	DCW	-1
	DCW	11
	DCW	176
	DCW	-1
	DCW	150
	DCW	74
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	58
	DCW	163
	DCW	-1
	DCW	89
	DCW	149
	DCW	-1
	DCW	42
	DCW	162
	DCW	-47
	DCW	-23
	DCW	-9
	DCW	-3
	DCW	-1
	DCW	26
	DCW	161
	DCW	-3
	DCW	-1
	DCW	10
	DCW	104
	DCW	160
	DCW	-5
	DCW	-3
	DCW	-1
	DCW	134
	DCW	73
	DCW	147
	DCW	-3
	DCW	-1
	DCW	57
	DCW	88
	DCW	-1
	DCW	133
	DCW	103
	DCW	-9
	DCW	-3
	DCW	-1
	DCW	41
	DCW	146
	DCW	-3
	DCW	-1
	DCW	87
	DCW	117
	DCW	56
	DCW	-5
	DCW	-1
	DCW	131
	DCW	-1
	DCW	102
	DCW	71
	DCW	-3
	DCW	-1
	DCW	116
	DCW	86
	DCW	-1
	DCW	101
	DCW	115
	DCW	-11
	DCW	-3
	DCW	-1
	DCW	25
	DCW	145
	DCW	-3
	DCW	-1
	DCW	9
	DCW	144
	DCW	-1
	DCW	72
	DCW	132
	DCW	-7
	DCW	-5
	DCW	-1
	DCW	114
	DCW	-1
	DCW	70
	DCW	100
	DCW	40
	DCW	-1
	DCW	130
	DCW	24
	DCW	-41
	DCW	-27
	DCW	-11
	DCW	-5
	DCW	-3
	DCW	-1
	DCW	55
	DCW	39
	DCW	23
	DCW	-1
	DCW	113
	DCW	-1
	DCW	85
	DCW	7
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	112
	DCW	54
	DCW	-1
	DCW	99
	DCW	69
	DCW	-3
	DCW	-1
	DCW	84
	DCW	38
	DCW	-1
	DCW	98
	DCW	53
	DCW	-5
	DCW	-1
	DCW	129
	DCW	-1
	DCW	8
	DCW	128
	DCW	-3
	DCW	-1
	DCW	22
	DCW	97
	DCW	-1
	DCW	6
	DCW	96
	DCW	-13
	DCW	-9
	DCW	-5
	DCW	-3
	DCW	-1
	DCW	83
	DCW	68
	DCW	37
	DCW	-1
	DCW	82
	DCW	5
	DCW	-1
	DCW	21
	DCW	81
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	52
	DCW	67
	DCW	-1
	DCW	80
	DCW	36
	DCW	-3
	DCW	-1
	DCW	66
	DCW	51
	DCW	20
	DCW	-19
	DCW	-11
	DCW	-5
	DCW	-1
	DCW	65
	DCW	-1
	DCW	4
	DCW	64
	DCW	-3
	DCW	-1
	DCW	35
	DCW	50
	DCW	19
	DCW	-3
	DCW	-1
	DCW	49
	DCW	3
	DCW	-1
	DCW	48
	DCW	34
	DCW	-3
	DCW	-1
	DCW	18
	DCW	33
	DCW	-1
	DCW	2
	DCW	32
	DCW	-3
	DCW	-1
	DCW	17
	DCW	1
	DCW	16
	DCW	0
	ALIGN 2
|tab15|
	KEEP |tab15|
	DCW	-495
	DCW	-445
	DCW	-355
	DCW	-263
	DCW	-183
	DCW	-115
	DCW	-77
	DCW	-43
	DCW	-27
	DCW	-13
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	255
	DCW	239
	DCW	-1
	DCW	254
	DCW	223
	DCW	-1
	DCW	238
	DCW	-1
	DCW	253
	DCW	207
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	252
	DCW	222
	DCW	-1
	DCW	237
	DCW	191
	DCW	-1
	DCW	251
	DCW	-1
	DCW	206
	DCW	236
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	221
	DCW	175
	DCW	-1
	DCW	250
	DCW	190
	DCW	-3
	DCW	-1
	DCW	235
	DCW	205
	DCW	-1
	DCW	220
	DCW	159
	DCW	-15
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	249
	DCW	234
	DCW	-1
	DCW	189
	DCW	219
	DCW	-3
	DCW	-1
	DCW	143
	DCW	248
	DCW	-1
	DCW	204
	DCW	158
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	233
	DCW	127
	DCW	-1
	DCW	247
	DCW	173
	DCW	-3
	DCW	-1
	DCW	218
	DCW	188
	DCW	-1
	DCW	111
	DCW	-1
	DCW	174
	DCW	15
	DCW	-19
	DCW	-11
	DCW	-3
	DCW	-1
	DCW	203
	DCW	246
	DCW	-3
	DCW	-1
	DCW	142
	DCW	232
	DCW	-1
	DCW	95
	DCW	157
	DCW	-3
	DCW	-1
	DCW	245
	DCW	126
	DCW	-1
	DCW	231
	DCW	172
	DCW	-9
	DCW	-3
	DCW	-1
	DCW	202
	DCW	187
	DCW	-3
	DCW	-1
	DCW	217
	DCW	141
	DCW	79
	DCW	-3
	DCW	-1
	DCW	244
	DCW	63
	DCW	-1
	DCW	243
	DCW	216
	DCW	-33
	DCW	-17
	DCW	-9
	DCW	-3
	DCW	-1
	DCW	230
	DCW	47
	DCW	-1
	DCW	242
	DCW	-1
	DCW	110
	DCW	240
	DCW	-3
	DCW	-1
	DCW	31
	DCW	241
	DCW	-1
	DCW	156
	DCW	201
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	94
	DCW	171
	DCW	-1
	DCW	186
	DCW	229
	DCW	-3
	DCW	-1
	DCW	125
	DCW	215
	DCW	-1
	DCW	78
	DCW	228
	DCW	-15
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	140
	DCW	200
	DCW	-1
	DCW	62
	DCW	109
	DCW	-3
	DCW	-1
	DCW	214
	DCW	227
	DCW	-1
	DCW	155
	DCW	185
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	46
	DCW	170
	DCW	-1
	DCW	226
	DCW	30
	DCW	-5
	DCW	-1
	DCW	225
	DCW	-1
	DCW	14
	DCW	224
	DCW	-1
	DCW	93
	DCW	213
	DCW	-45
	DCW	-25
	DCW	-13
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	124
	DCW	199
	DCW	-1
	DCW	77
	DCW	139
	DCW	-1
	DCW	212
	DCW	-1
	DCW	184
	DCW	154
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	169
	DCW	108
	DCW	-1
	DCW	198
	DCW	61
	DCW	-1
	DCW	211
	DCW	210
	DCW	-9
	DCW	-5
	DCW	-3
	DCW	-1
	DCW	45
	DCW	13
	DCW	29
	DCW	-1
	DCW	123
	DCW	183
	DCW	-5
	DCW	-1
	DCW	209
	DCW	-1
	DCW	92
	DCW	208
	DCW	-1
	DCW	197
	DCW	138
	DCW	-17
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	168
	DCW	76
	DCW	-1
	DCW	196
	DCW	107
	DCW	-5
	DCW	-1
	DCW	182
	DCW	-1
	DCW	153
	DCW	12
	DCW	-1
	DCW	60
	DCW	195
	DCW	-9
	DCW	-3
	DCW	-1
	DCW	122
	DCW	167
	DCW	-1
	DCW	166
	DCW	-1
	DCW	192
	DCW	11
	DCW	-1
	DCW	194
	DCW	-1
	DCW	44
	DCW	91
	DCW	-55
	DCW	-29
	DCW	-15
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	181
	DCW	28
	DCW	-1
	DCW	137
	DCW	152
	DCW	-3
	DCW	-1
	DCW	193
	DCW	75
	DCW	-1
	DCW	180
	DCW	106
	DCW	-5
	DCW	-3
	DCW	-1
	DCW	59
	DCW	121
	DCW	179
	DCW	-3
	DCW	-1
	DCW	151
	DCW	136
	DCW	-1
	DCW	43
	DCW	90
	DCW	-11
	DCW	-5
	DCW	-1
	DCW	178
	DCW	-1
	DCW	165
	DCW	27
	DCW	-1
	DCW	177
	DCW	-1
	DCW	176
	DCW	105
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	150
	DCW	74
	DCW	-1
	DCW	164
	DCW	120
	DCW	-3
	DCW	-1
	DCW	135
	DCW	58
	DCW	163
	DCW	-17
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	89
	DCW	149
	DCW	-1
	DCW	42
	DCW	162
	DCW	-3
	DCW	-1
	DCW	26
	DCW	161
	DCW	-3
	DCW	-1
	DCW	10
	DCW	160
	DCW	104
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	134
	DCW	73
	DCW	-1
	DCW	148
	DCW	57
	DCW	-5
	DCW	-1
	DCW	147
	DCW	-1
	DCW	119
	DCW	9
	DCW	-1
	DCW	88
	DCW	133
	DCW	-53
	DCW	-29
	DCW	-13
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	41
	DCW	103
	DCW	-1
	DCW	118
	DCW	146
	DCW	-1
	DCW	145
	DCW	-1
	DCW	25
	DCW	144
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	72
	DCW	132
	DCW	-1
	DCW	87
	DCW	117
	DCW	-3
	DCW	-1
	DCW	56
	DCW	131
	DCW	-1
	DCW	102
	DCW	71
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	40
	DCW	130
	DCW	-1
	DCW	24
	DCW	129
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	116
	DCW	8
	DCW	-1
	DCW	128
	DCW	86
	DCW	-3
	DCW	-1
	DCW	101
	DCW	55
	DCW	-1
	DCW	115
	DCW	70
	DCW	-17
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	39
	DCW	114
	DCW	-1
	DCW	100
	DCW	23
	DCW	-3
	DCW	-1
	DCW	85
	DCW	113
	DCW	-3
	DCW	-1
	DCW	7
	DCW	112
	DCW	54
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	99
	DCW	69
	DCW	-1
	DCW	84
	DCW	38
	DCW	-3
	DCW	-1
	DCW	98
	DCW	22
	DCW	-3
	DCW	-1
	DCW	6
	DCW	96
	DCW	53
	DCW	-33
	DCW	-19
	DCW	-9
	DCW	-5
	DCW	-1
	DCW	97
	DCW	-1
	DCW	83
	DCW	68
	DCW	-1
	DCW	37
	DCW	82
	DCW	-3
	DCW	-1
	DCW	21
	DCW	81
	DCW	-3
	DCW	-1
	DCW	5
	DCW	80
	DCW	52
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	67
	DCW	36
	DCW	-1
	DCW	66
	DCW	51
	DCW	-1
	DCW	65
	DCW	-1
	DCW	20
	DCW	4
	DCW	-9
	DCW	-3
	DCW	-1
	DCW	35
	DCW	50
	DCW	-3
	DCW	-1
	DCW	64
	DCW	3
	DCW	19
	DCW	-3
	DCW	-1
	DCW	49
	DCW	48
	DCW	34
	DCW	-9
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	18
	DCW	33
	DCW	-1
	DCW	2
	DCW	32
	DCW	17
	DCW	-3
	DCW	-1
	DCW	1
	DCW	16
	DCW	0
	ALIGN 2
|tab16|
	KEEP |tab16|
	DCW	-509
	DCW	-503
	DCW	-461
	DCW	-323
	DCW	-103
	DCW	-37
	DCW	-27
	DCW	-15
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	239
	DCW	254
	DCW	-1
	DCW	223
	DCW	253
	DCW	-3
	DCW	-1
	DCW	207
	DCW	252
	DCW	-1
	DCW	191
	DCW	251
	DCW	-5
	DCW	-1
	DCW	175
	DCW	-1
	DCW	250
	DCW	159
	DCW	-3
	DCW	-1
	DCW	249
	DCW	248
	DCW	143
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	127
	DCW	247
	DCW	-1
	DCW	111
	DCW	246
	DCW	255
	DCW	-9
	DCW	-5
	DCW	-3
	DCW	-1
	DCW	95
	DCW	245
	DCW	79
	DCW	-1
	DCW	244
	DCW	243
	DCW	-53
	DCW	-1
	DCW	240
	DCW	-1
	DCW	63
	DCW	-29
	DCW	-19
	DCW	-13
	DCW	-7
	DCW	-5
	DCW	-1
	DCW	206
	DCW	-1
	DCW	236
	DCW	221
	DCW	222
	DCW	-1
	DCW	233
	DCW	-1
	DCW	234
	DCW	217
	DCW	-1
	DCW	238
	DCW	-1
	DCW	237
	DCW	235
	DCW	-3
	DCW	-1
	DCW	190
	DCW	205
	DCW	-3
	DCW	-1
	DCW	220
	DCW	219
	DCW	174
	DCW	-11
	DCW	-5
	DCW	-1
	DCW	204
	DCW	-1
	DCW	173
	DCW	218
	DCW	-3
	DCW	-1
	DCW	126
	DCW	172
	DCW	202
	DCW	-5
	DCW	-3
	DCW	-1
	DCW	201
	DCW	125
	DCW	94
	DCW	189
	DCW	242
	DCW	-93
	DCW	-5
	DCW	-3
	DCW	-1
	DCW	47
	DCW	15
	DCW	31
	DCW	-1
	DCW	241
	DCW	-49
	DCW	-25
	DCW	-13
	DCW	-5
	DCW	-1
	DCW	158
	DCW	-1
	DCW	188
	DCW	203
	DCW	-3
	DCW	-1
	DCW	142
	DCW	232
	DCW	-1
	DCW	157
	DCW	231
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	187
	DCW	141
	DCW	-1
	DCW	216
	DCW	110
	DCW	-1
	DCW	230
	DCW	156
	DCW	-13
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	171
	DCW	186
	DCW	-1
	DCW	229
	DCW	215
	DCW	-1
	DCW	78
	DCW	-1
	DCW	228
	DCW	140
	DCW	-3
	DCW	-1
	DCW	200
	DCW	62
	DCW	-1
	DCW	109
	DCW	-1
	DCW	214
	DCW	155
	DCW	-19
	DCW	-11
	DCW	-5
	DCW	-3
	DCW	-1
	DCW	185
	DCW	170
	DCW	225
	DCW	-1
	DCW	212
	DCW	-1
	DCW	184
	DCW	169
	DCW	-5
	DCW	-1
	DCW	123
	DCW	-1
	DCW	183
	DCW	208
	DCW	227
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	14
	DCW	224
	DCW	-1
	DCW	93
	DCW	213
	DCW	-3
	DCW	-1
	DCW	124
	DCW	199
	DCW	-1
	DCW	77
	DCW	139
	DCW	-75
	DCW	-45
	DCW	-27
	DCW	-13
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	154
	DCW	108
	DCW	-1
	DCW	198
	DCW	61
	DCW	-3
	DCW	-1
	DCW	92
	DCW	197
	DCW	13
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	138
	DCW	168
	DCW	-1
	DCW	153
	DCW	76
	DCW	-3
	DCW	-1
	DCW	182
	DCW	122
	DCW	60
	DCW	-11
	DCW	-5
	DCW	-3
	DCW	-1
	DCW	91
	DCW	137
	DCW	28
	DCW	-1
	DCW	192
	DCW	-1
	DCW	152
	DCW	121
	DCW	-1
	DCW	226
	DCW	-1
	DCW	46
	DCW	30
	DCW	-15
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	211
	DCW	45
	DCW	-1
	DCW	210
	DCW	209
	DCW	-5
	DCW	-1
	DCW	59
	DCW	-1
	DCW	151
	DCW	136
	DCW	29
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	196
	DCW	107
	DCW	-1
	DCW	195
	DCW	167
	DCW	-1
	DCW	44
	DCW	-1
	DCW	194
	DCW	181
	DCW	-23
	DCW	-13
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	193
	DCW	12
	DCW	-1
	DCW	75
	DCW	180
	DCW	-3
	DCW	-1
	DCW	106
	DCW	166
	DCW	179
	DCW	-5
	DCW	-3
	DCW	-1
	DCW	90
	DCW	165
	DCW	43
	DCW	-1
	DCW	178
	DCW	27
	DCW	-13
	DCW	-5
	DCW	-1
	DCW	177
	DCW	-1
	DCW	11
	DCW	176
	DCW	-3
	DCW	-1
	DCW	105
	DCW	150
	DCW	-1
	DCW	74
	DCW	164
	DCW	-5
	DCW	-3
	DCW	-1
	DCW	120
	DCW	135
	DCW	163
	DCW	-3
	DCW	-1
	DCW	58
	DCW	89
	DCW	42
	DCW	-97
	DCW	-57
	DCW	-33
	DCW	-19
	DCW	-11
	DCW	-5
	DCW	-3
	DCW	-1
	DCW	149
	DCW	104
	DCW	161
	DCW	-3
	DCW	-1
	DCW	134
	DCW	119
	DCW	148
	DCW	-5
	DCW	-3
	DCW	-1
	DCW	73
	DCW	87
	DCW	103
	DCW	162
	DCW	-5
	DCW	-1
	DCW	26
	DCW	-1
	DCW	10
	DCW	160
	DCW	-3
	DCW	-1
	DCW	57
	DCW	147
	DCW	-1
	DCW	88
	DCW	133
	DCW	-9
	DCW	-3
	DCW	-1
	DCW	41
	DCW	146
	DCW	-3
	DCW	-1
	DCW	118
	DCW	9
	DCW	25
	DCW	-5
	DCW	-1
	DCW	145
	DCW	-1
	DCW	144
	DCW	72
	DCW	-3
	DCW	-1
	DCW	132
	DCW	117
	DCW	-1
	DCW	56
	DCW	131
	DCW	-21
	DCW	-11
	DCW	-5
	DCW	-3
	DCW	-1
	DCW	102
	DCW	40
	DCW	130
	DCW	-3
	DCW	-1
	DCW	71
	DCW	116
	DCW	24
	DCW	-3
	DCW	-1
	DCW	129
	DCW	128
	DCW	-3
	DCW	-1
	DCW	8
	DCW	86
	DCW	55
	DCW	-9
	DCW	-5
	DCW	-1
	DCW	115
	DCW	-1
	DCW	101
	DCW	70
	DCW	-1
	DCW	39
	DCW	114
	DCW	-5
	DCW	-3
	DCW	-1
	DCW	100
	DCW	85
	DCW	7
	DCW	23
	DCW	-23
	DCW	-13
	DCW	-5
	DCW	-1
	DCW	113
	DCW	-1
	DCW	112
	DCW	54
	DCW	-3
	DCW	-1
	DCW	99
	DCW	69
	DCW	-1
	DCW	84
	DCW	38
	DCW	-3
	DCW	-1
	DCW	98
	DCW	22
	DCW	-1
	DCW	97
	DCW	-1
	DCW	6
	DCW	96
	DCW	-9
	DCW	-5
	DCW	-1
	DCW	83
	DCW	-1
	DCW	53
	DCW	68
	DCW	-1
	DCW	37
	DCW	82
	DCW	-1
	DCW	81
	DCW	-1
	DCW	21
	DCW	5
	DCW	-33
	DCW	-23
	DCW	-13
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	52
	DCW	67
	DCW	-1
	DCW	80
	DCW	36
	DCW	-3
	DCW	-1
	DCW	66
	DCW	51
	DCW	20
	DCW	-5
	DCW	-1
	DCW	65
	DCW	-1
	DCW	4
	DCW	64
	DCW	-1
	DCW	35
	DCW	50
	DCW	-3
	DCW	-1
	DCW	19
	DCW	49
	DCW	-3
	DCW	-1
	DCW	3
	DCW	48
	DCW	34
	DCW	-3
	DCW	-1
	DCW	18
	DCW	33
	DCW	-1
	DCW	2
	DCW	32
	DCW	-3
	DCW	-1
	DCW	17
	DCW	1
	DCW	16
	DCW	0
	ALIGN 2
|tab24|
	KEEP |tab24|
	DCW	-451
	DCW	-117
	DCW	-43
	DCW	-25
	DCW	-15
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	239
	DCW	254
	DCW	-1
	DCW	223
	DCW	253
	DCW	-3
	DCW	-1
	DCW	207
	DCW	252
	DCW	-1
	DCW	191
	DCW	251
	DCW	-5
	DCW	-1
	DCW	250
	DCW	-1
	DCW	175
	DCW	159
	DCW	-1
	DCW	249
	DCW	248
	DCW	-9
	DCW	-5
	DCW	-3
	DCW	-1
	DCW	143
	DCW	127
	DCW	247
	DCW	-1
	DCW	111
	DCW	246
	DCW	-3
	DCW	-1
	DCW	95
	DCW	245
	DCW	-1
	DCW	79
	DCW	244
	DCW	-71
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	63
	DCW	243
	DCW	-1
	DCW	47
	DCW	242
	DCW	-5
	DCW	-1
	DCW	241
	DCW	-1
	DCW	31
	DCW	240
	DCW	-25
	DCW	-9
	DCW	-1
	DCW	15
	DCW	-3
	DCW	-1
	DCW	238
	DCW	222
	DCW	-1
	DCW	237
	DCW	206
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	236
	DCW	221
	DCW	-1
	DCW	190
	DCW	235
	DCW	-3
	DCW	-1
	DCW	205
	DCW	220
	DCW	-1
	DCW	174
	DCW	234
	DCW	-15
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	189
	DCW	219
	DCW	-1
	DCW	204
	DCW	158
	DCW	-3
	DCW	-1
	DCW	233
	DCW	173
	DCW	-1
	DCW	218
	DCW	188
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	203
	DCW	142
	DCW	-1
	DCW	232
	DCW	157
	DCW	-3
	DCW	-1
	DCW	217
	DCW	126
	DCW	-1
	DCW	231
	DCW	172
	DCW	255
	DCW	-235
	DCW	-143
	DCW	-77
	DCW	-45
	DCW	-25
	DCW	-15
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	202
	DCW	187
	DCW	-1
	DCW	141
	DCW	216
	DCW	-5
	DCW	-3
	DCW	-1
	DCW	14
	DCW	224
	DCW	13
	DCW	230
	DCW	-5
	DCW	-3
	DCW	-1
	DCW	110
	DCW	156
	DCW	201
	DCW	-1
	DCW	94
	DCW	186
	DCW	-9
	DCW	-5
	DCW	-1
	DCW	229
	DCW	-1
	DCW	171
	DCW	125
	DCW	-1
	DCW	215
	DCW	228
	DCW	-3
	DCW	-1
	DCW	140
	DCW	200
	DCW	-3
	DCW	-1
	DCW	78
	DCW	46
	DCW	62
	DCW	-15
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	109
	DCW	214
	DCW	-1
	DCW	227
	DCW	155
	DCW	-3
	DCW	-1
	DCW	185
	DCW	170
	DCW	-1
	DCW	226
	DCW	30
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	225
	DCW	93
	DCW	-1
	DCW	213
	DCW	124
	DCW	-3
	DCW	-1
	DCW	199
	DCW	77
	DCW	-1
	DCW	139
	DCW	184
	DCW	-31
	DCW	-15
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	212
	DCW	154
	DCW	-1
	DCW	169
	DCW	108
	DCW	-3
	DCW	-1
	DCW	198
	DCW	61
	DCW	-1
	DCW	211
	DCW	45
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	210
	DCW	29
	DCW	-1
	DCW	123
	DCW	183
	DCW	-3
	DCW	-1
	DCW	209
	DCW	92
	DCW	-1
	DCW	197
	DCW	138
	DCW	-17
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	168
	DCW	153
	DCW	-1
	DCW	76
	DCW	196
	DCW	-3
	DCW	-1
	DCW	107
	DCW	182
	DCW	-3
	DCW	-1
	DCW	208
	DCW	12
	DCW	60
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	195
	DCW	122
	DCW	-1
	DCW	167
	DCW	44
	DCW	-3
	DCW	-1
	DCW	194
	DCW	91
	DCW	-1
	DCW	181
	DCW	28
	DCW	-57
	DCW	-35
	DCW	-19
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	137
	DCW	152
	DCW	-1
	DCW	193
	DCW	75
	DCW	-5
	DCW	-3
	DCW	-1
	DCW	192
	DCW	11
	DCW	59
	DCW	-3
	DCW	-1
	DCW	176
	DCW	10
	DCW	26
	DCW	-5
	DCW	-1
	DCW	180
	DCW	-1
	DCW	106
	DCW	166
	DCW	-3
	DCW	-1
	DCW	121
	DCW	151
	DCW	-3
	DCW	-1
	DCW	160
	DCW	9
	DCW	144
	DCW	-9
	DCW	-3
	DCW	-1
	DCW	179
	DCW	136
	DCW	-3
	DCW	-1
	DCW	43
	DCW	90
	DCW	178
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	165
	DCW	27
	DCW	-1
	DCW	177
	DCW	105
	DCW	-1
	DCW	150
	DCW	164
	DCW	-17
	DCW	-9
	DCW	-5
	DCW	-3
	DCW	-1
	DCW	74
	DCW	120
	DCW	135
	DCW	-1
	DCW	58
	DCW	163
	DCW	-3
	DCW	-1
	DCW	89
	DCW	149
	DCW	-1
	DCW	42
	DCW	162
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	161
	DCW	104
	DCW	-1
	DCW	134
	DCW	119
	DCW	-3
	DCW	-1
	DCW	73
	DCW	148
	DCW	-1
	DCW	57
	DCW	147
	DCW	-63
	DCW	-31
	DCW	-15
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	88
	DCW	133
	DCW	-1
	DCW	41
	DCW	103
	DCW	-3
	DCW	-1
	DCW	118
	DCW	146
	DCW	-1
	DCW	25
	DCW	145
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	72
	DCW	132
	DCW	-1
	DCW	87
	DCW	117
	DCW	-3
	DCW	-1
	DCW	56
	DCW	131
	DCW	-1
	DCW	102
	DCW	40
	DCW	-17
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	130
	DCW	24
	DCW	-1
	DCW	71
	DCW	116
	DCW	-5
	DCW	-1
	DCW	129
	DCW	-1
	DCW	8
	DCW	128
	DCW	-1
	DCW	86
	DCW	101
	DCW	-7
	DCW	-5
	DCW	-1
	DCW	23
	DCW	-1
	DCW	7
	DCW	112
	DCW	115
	DCW	-3
	DCW	-1
	DCW	55
	DCW	39
	DCW	114
	DCW	-15
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	70
	DCW	100
	DCW	-1
	DCW	85
	DCW	113
	DCW	-3
	DCW	-1
	DCW	54
	DCW	99
	DCW	-1
	DCW	69
	DCW	84
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	38
	DCW	98
	DCW	-1
	DCW	22
	DCW	97
	DCW	-5
	DCW	-3
	DCW	-1
	DCW	6
	DCW	96
	DCW	53
	DCW	-1
	DCW	83
	DCW	68
	DCW	-51
	DCW	-37
	DCW	-23
	DCW	-15
	DCW	-9
	DCW	-3
	DCW	-1
	DCW	37
	DCW	82
	DCW	-1
	DCW	21
	DCW	-1
	DCW	5
	DCW	80
	DCW	-1
	DCW	81
	DCW	-1
	DCW	52
	DCW	67
	DCW	-3
	DCW	-1
	DCW	36
	DCW	66
	DCW	-1
	DCW	51
	DCW	20
	DCW	-9
	DCW	-5
	DCW	-1
	DCW	65
	DCW	-1
	DCW	4
	DCW	64
	DCW	-1
	DCW	35
	DCW	50
	DCW	-1
	DCW	19
	DCW	49
	DCW	-7
	DCW	-5
	DCW	-3
	DCW	-1
	DCW	3
	DCW	48
	DCW	34
	DCW	18
	DCW	-1
	DCW	33
	DCW	-1
	DCW	2
	DCW	32
	DCW	-3
	DCW	-1
	DCW	17
	DCW	1
	DCW	-1
	DCW	16
	DCW	0
	ALIGN 2
|tab_c0|
	KEEP |tab_c0|
	DCW	-29
	DCW	-21
	DCW	-13
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	11
	DCW	15
	DCW	-1
	DCW	13
	DCW	14
	DCW	-3
	DCW	-1
	DCW	7
	DCW	5
	DCW	9
	DCW	-3
	DCW	-1
	DCW	6
	DCW	3
	DCW	-1
	DCW	10
	DCW	12
	DCW	-3
	DCW	-1
	DCW	2
	DCW	1
	DCW	-1
	DCW	4
	DCW	8
	DCW	0
	ALIGN 2
|tab_c1|
	KEEP |tab_c1|
	DCW	-15
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	15
	DCW	14
	DCW	-1
	DCW	13
	DCW	12
	DCW	-3
	DCW	-1
	DCW	11
	DCW	10
	DCW	-1
	DCW	9
	DCW	8
	DCW	-7
	DCW	-3
	DCW	-1
	DCW	7
	DCW	6
	DCW	-1
	DCW	5
	DCW	4
	DCW	-3
	DCW	-1
	DCW	3
	DCW	2
	DCW	-1
	DCW	1
	DCW	0
	ALIGN
|ht|
	KEEP |ht|
	DCD	0
	DCD	|tab0|
	DCD	0
	DCD	|tab1|
	DCD	0
	DCD	|tab2|
	DCD	0
	DCD	|tab3|
	DCD	0
	DCD	|tab0|
	DCD	0
	DCD	|tab5|
	DCD	0
	DCD	|tab6|
	DCD	0
	DCD	|tab7|
	DCD	0
	DCD	|tab8|
	DCD	0
	DCD	|tab9|
	DCD	0
	DCD	|tab10|
	DCD	0
	DCD	|tab11|
	DCD	0
	DCD	|tab12|
	DCD	0
	DCD	|tab13|
	DCD	0
	DCD	|tab0|
	DCD	0
	DCD	|tab15|
	DCD	1
	DCD	|tab16|
	DCD	2
	DCD	|tab16|
	DCD	3
	DCD	|tab16|
	DCD	4
	DCD	|tab16|
	DCD	6
	DCD	|tab16|
	DCD	8
	DCD	|tab16|
	DCD	10
	DCD	|tab16|
	DCD	13
	DCD	|tab16|
	DCD	4
	DCD	|tab24|
	DCD	5
	DCD	|tab24|
	DCD	6
	DCD	|tab24|
	DCD	7
	DCD	|tab24|
	DCD	8
	DCD	|tab24|
	DCD	9
	DCD	|tab24|
	DCD	11
	DCD	|tab24|
	DCD	13
	DCD	|tab24|
	ALIGN
|htc|
	KEEP |htc|
	DCD	0
	DCD	|tab_c0|
	DCD	0
	DCD	|tab_c1|
	EXPORT	|bandInfo|
	ALIGN
|bandInfo|
	DCW	0
	DCW	4
	DCW	8
	DCW	12
	DCW	16
	DCW	20
	DCW	24
	DCW	30
	DCW	36
	DCW	44
	DCW	52
	DCW	62
	DCW	74
	DCW	90
	DCW	110
	DCW	134
	DCW	162
	DCW	196
	DCW	238
	DCW	288
	DCW	342
	DCW	418
	DCW	576
	DCW	4
	DCW	4
	DCW	4
	DCW	4
	DCW	4
	DCW	4
	DCW	6
	DCW	6
	DCW	8
	DCW	8
	DCW	10
	DCW	12
	DCW	16
	DCW	20
	DCW	24
	DCW	28
	DCW	34
	DCW	42
	DCW	50
	DCW	54
	DCW	76
	DCW	158
	DCW	0
	DCW	12
	DCW	24
	DCW	36
	DCW	48
	DCW	66
	DCW	90
	DCW	120
	DCW	156
	DCW	198
	DCW	252
	DCW	318
	DCW	408
	DCW	576
	DCW	4
	DCW	4
	DCW	4
	DCW	4
	DCW	6
	DCW	8
	DCW	10
	DCW	12
	DCW	14
	DCW	18
	DCW	22
	DCW	30
	DCW	56
	DCW	0
	DCW	4
	DCW	8
	DCW	12
	DCW	16
	DCW	20
	DCW	24
	DCW	30
	DCW	36
	DCW	42
	DCW	50
	DCW	60
	DCW	72
	DCW	88
	DCW	106
	DCW	128
	DCW	156
	DCW	190
	DCW	230
	DCW	276
	DCW	330
	DCW	384
	DCW	576
	DCW	4
	DCW	4
	DCW	4
	DCW	4
	DCW	4
	DCW	4
	DCW	6
	DCW	6
	DCW	6
	DCW	8
	DCW	10
	DCW	12
	DCW	16
	DCW	18
	DCW	22
	DCW	28
	DCW	34
	DCW	40
	DCW	46
	DCW	54
	DCW	54
	DCW	192
	DCW	0
	DCW	12
	DCW	24
	DCW	36
	DCW	48
	DCW	66
	DCW	84
	DCW	114
	DCW	150
	DCW	192
	DCW	240
	DCW	300
	DCW	378
	DCW	576
	DCW	4
	DCW	4
	DCW	4
	DCW	4
	DCW	6
	DCW	6
	DCW	10
	DCW	12
	DCW	14
	DCW	16
	DCW	20
	DCW	26
	DCW	66
	DCW	0
	DCW	4
	DCW	8
	DCW	12
	DCW	16
	DCW	20
	DCW	24
	DCW	30
	DCW	36
	DCW	44
	DCW	54
	DCW	66
	DCW	82
	DCW	102
	DCW	126
	DCW	156
	DCW	194
	DCW	240
	DCW	296
	DCW	364
	DCW	448
	DCW	550
	DCW	576
	DCW	4
	DCW	4
	DCW	4
	DCW	4
	DCW	4
	DCW	4
	DCW	6
	DCW	6
	DCW	8
	DCW	10
	DCW	12
	DCW	16
	DCW	20
	DCW	24
	DCW	30
	DCW	38
	DCW	46
	DCW	56
	DCW	68
	DCW	84
	DCW	102
	DCW	26
	DCW	0
	DCW	12
	DCW	24
	DCW	36
	DCW	48
	DCW	66
	DCW	90
	DCW	126
	DCW	174
	DCW	234
	DCW	312
	DCW	414
	DCW	540
	DCW	576
	DCW	4
	DCW	4
	DCW	4
	DCW	4
	DCW	6
	DCW	8
	DCW	12
	DCW	16
	DCW	20
	DCW	26
	DCW	34
	DCW	42
	DCW	12
	DCW	0
	DCW	6
	DCW	12
	DCW	18
	DCW	24
	DCW	30
	DCW	36
	DCW	44
	DCW	54
	DCW	66
	DCW	80
	DCW	96
	DCW	116
	DCW	140
	DCW	168
	DCW	200
	DCW	238
	DCW	284
	DCW	336
	DCW	396
	DCW	464
	DCW	522
	DCW	576
	DCW	6
	DCW	6
	DCW	6
	DCW	6
	DCW	6
	DCW	6
	DCW	8
	DCW	10
	DCW	12
	DCW	14
	DCW	16
	DCW	20
	DCW	24
	DCW	28
	DCW	32
	DCW	38
	DCW	46
	DCW	52
	DCW	60
	DCW	68
	DCW	58
	DCW	54
	DCW	0
	DCW	12
	DCW	24
	DCW	36
	DCW	54
	DCW	72
	DCW	96
	DCW	126
	DCW	168
	DCW	222
	DCW	300
	DCW	396
	DCW	522
	DCW	576
	DCW	4
	DCW	4
	DCW	4
	DCW	6
	DCW	6
	DCW	8
	DCW	10
	DCW	14
	DCW	18
	DCW	26
	DCW	32
	DCW	42
	DCW	18
	DCW	0
	DCW	6
	DCW	12
	DCW	18
	DCW	24
	DCW	30
	DCW	36
	DCW	44
	DCW	54
	DCW	66
	DCW	80
	DCW	96
	DCW	114
	DCW	136
	DCW	162
	DCW	194
	DCW	232
	DCW	278
	DCW	332
	DCW	394
	DCW	464
	DCW	540
	DCW	576
	DCW	6
	DCW	6
	DCW	6
	DCW	6
	DCW	6
	DCW	6
	DCW	8
	DCW	10
	DCW	12
	DCW	14
	DCW	16
	DCW	18
	DCW	22
	DCW	26
	DCW	32
	DCW	38
	DCW	46
	DCW	54
	DCW	62
	DCW	70
	DCW	76
	DCW	36
	DCW	0
	DCW	12
	DCW	24
	DCW	36
	DCW	54
	DCW	78
	DCW	108
	DCW	144
	DCW	186
	DCW	240
	DCW	312
	DCW	408
	DCW	540
	DCW	576
	DCW	4
	DCW	4
	DCW	4
	DCW	6
	DCW	8
	DCW	10
	DCW	12
	DCW	14
	DCW	18
	DCW	24
	DCW	32
	DCW	44
	DCW	12
	DCW	0
	DCW	6
	DCW	12
	DCW	18
	DCW	24
	DCW	30
	DCW	36
	DCW	44
	DCW	54
	DCW	66
	DCW	80
	DCW	96
	DCW	116
	DCW	140
	DCW	168
	DCW	200
	DCW	238
	DCW	284
	DCW	336
	DCW	396
	DCW	464
	DCW	522
	DCW	576
	DCW	6
	DCW	6
	DCW	6
	DCW	6
	DCW	6
	DCW	6
	DCW	8
	DCW	10
	DCW	12
	DCW	14
	DCW	16
	DCW	20
	DCW	24
	DCW	28
	DCW	32
	DCW	38
	DCW	46
	DCW	52
	DCW	60
	DCW	68
	DCW	58
	DCW	54
	DCW	0
	DCW	12
	DCW	24
	DCW	36
	DCW	54
	DCW	78
	DCW	108
	DCW	144
	DCW	186
	DCW	240
	DCW	312
	DCW	402
	DCW	522
	DCW	576
	DCW	4
	DCW	4
	DCW	4
	DCW	6
	DCW	8
	DCW	10
	DCW	12
	DCW	14
	DCW	18
	DCW	24
	DCW	30
	DCW	40
	DCW	18
	DCW	0
	DCW	6
	DCW	12
	DCW	18
	DCW	24
	DCW	30
	DCW	36
	DCW	44
	DCW	54
	DCW	66
	DCW	80
	DCW	96
	DCW	116
	DCW	140
	DCW	168
	DCW	200
	DCW	238
	DCW	284
	DCW	336
	DCW	396
	DCW	464
	DCW	522
	DCW	576
	DCW	6
	DCW	6
	DCW	6
	DCW	6
	DCW	6
	DCW	6
	DCW	8
	DCW	10
	DCW	12
	DCW	14
	DCW	16
	DCW	20
	DCW	24
	DCW	28
	DCW	32
	DCW	38
	DCW	46
	DCW	52
	DCW	60
	DCW	68
	DCW	58
	DCW	54
	DCW	0
	DCW	12
	DCW	24
	DCW	36
	DCW	54
	DCW	78
	DCW	108
	DCW	144
	DCW	186
	DCW	240
	DCW	312
	DCW	402
	DCW	522
	DCW	576
	DCW	4
	DCW	4
	DCW	4
	DCW	6
	DCW	8
	DCW	10
	DCW	12
	DCW	14
	DCW	18
	DCW	24
	DCW	30
	DCW	40
	DCW	18
	DCW	0
	DCW	6
	DCW	12
	DCW	18
	DCW	24
	DCW	30
	DCW	36
	DCW	44
	DCW	54
	DCW	66
	DCW	80
	DCW	96
	DCW	116
	DCW	140
	DCW	168
	DCW	200
	DCW	238
	DCW	284
	DCW	336
	DCW	396
	DCW	464
	DCW	522
	DCW	576
	DCW	6
	DCW	6
	DCW	6
	DCW	6
	DCW	6
	DCW	6
	DCW	8
	DCW	10
	DCW	12
	DCW	14
	DCW	16
	DCW	20
	DCW	24
	DCW	28
	DCW	32
	DCW	38
	DCW	46
	DCW	52
	DCW	60
	DCW	68
	DCW	58
	DCW	54
	DCW	0
	DCW	12
	DCW	24
	DCW	36
	DCW	54
	DCW	78
	DCW	108
	DCW	144
	DCW	186
	DCW	240
	DCW	312
	DCW	402
	DCW	522
	DCW	576
	DCW	4
	DCW	4
	DCW	4
	DCW	6
	DCW	8
	DCW	10
	DCW	12
	DCW	14
	DCW	18
	DCW	24
	DCW	30
	DCW	40
	DCW	18
	DCW	0
	DCW	12
	DCW	24
	DCW	36
	DCW	48
	DCW	60
	DCW	72
	DCW	88
	DCW	108
	DCW	132
	DCW	160
	DCW	192
	DCW	232
	DCW	280
	DCW	336
	DCW	400
	DCW	476
	DCW	566
	DCW	568
	DCW	570
	DCW	572
	DCW	574
	DCW	576
	DCW	12
	DCW	12
	DCW	12
	DCW	12
	DCW	12
	DCW	12
	DCW	16
	DCW	20
	DCW	24
	DCW	28
	DCW	32
	DCW	40
	DCW	48
	DCW	56
	DCW	64
	DCW	76
	DCW	90
	DCW	2
	DCW	2
	DCW	2
	DCW	2
	DCW	2
	DCW	0
	DCW	24
	DCW	48
	DCW	72
	DCW	108
	DCW	156
	DCW	216
	DCW	288
	DCW	372
	DCW	480
	DCW	486
	DCW	492
	DCW	498
	DCW	576
	DCW	8
	DCW	8
	DCW	8
	DCW	12
	DCW	16
	DCW	20
	DCW	24
	DCW	28
	DCW	36
	DCW	2
	DCW	2
	DCW	2
	DCW	26
	AREA |C$$data1|, DATA
	ALIGN
|Ci.6|
	KEEP |Ci.6|
	DCD &bfe33333, &33333333	; double -5.99999999999999977796e-1
	DCD &bfe11eb8, &51eb851f	; double -5.35000000000000031086e-1
	DCD &bfd51eb8, &51eb851f	; double -3.30000000000000015543e-1
	DCD &bfc7ae14, &7ae147ae	; double -1.84999999999999997780e-1
	DCD &bfb851eb, &851eb852	; double -9.50000000000000011102e-2
	DCD &bfa4fdf3, &b645a1cb	; double -4.10000000000000017208e-2
	DCD &bf8d14e3, &bcd35a86	; double -1.42000000000000008160e-2
	DCD &bf6e4f76, &5fd8adac	; double -3.70000000000000016376e-3
	ALIGN
|len.7|
	KEEP |len.7|
	DCD	36
	DCD	36
	DCD	12
	DCD	36
	AREA |C$$code2|, CODE, READONLY
	ALIGN
	EXPORT	|init_layer3|
|init_layer3|
	; args = 0, pretend = 0, frame = 28, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	bllt	|__rt_stkovf_split_small|
	sub	__sp, __sp, #28
	ldr	__v1, |L..210|
	ldr	__v2, |L..210|+4
	mvn	__v6, #255
	str	__a1, [__sp, #0]
|L..7|
	add	__a1, __v6, #210
	bl	|__floatsidf|
	adr	__a3, |L..210|+8
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	adr	__a1, |L..210|+16
	ldmia	__a1, {__a1-__a2}
	bl	|pow|
	add	__ip, __v6, #256
	add	__v6, __v6, #1
	cmp	__v6, #121
	add	__ip, __v1, __ip, asl #3
	stmia	__ip, {__a1-__a2}
	ble	|L..7|
	mov	__v6, #0
|L..12|
	mov	__a1, __v6
	bl	|__floatsidf|
	adr	__a3, |L..210|+24
	ldmia	__a3, {__a3-__a4}
	bl	|pow|
	add	__ip, __v2, __v6, asl #3
	ldr	__a3, |L..210|+32
	add	__v6, __v6, #1
	stmia	__ip, {__a1-__a2}
	cmp	__v6, __a3
	ble	|L..12|
	mov	__v6, #0
|L..17|
	ldr	__a1, |L..210|+36
	mov	__v5, __v6, asl #3
	add	__ip, __v5, __a1
	ldmia	__ip, {__v3-__v4}
	mov	__a2, __v4
	mov	__a1, __v3
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__muldf3|
	adr	__a3, |L..210|+40
	ldmia	__a3, {__a3-__a4}
	bl	|__adddf3|
	bl	|sqrt|
	mov	__v2, __a2
	mov	__v1, __a1
	adr	__a1, |L..210|+40
	ldmia	__a1, {__a1-__a2}
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__divdf3|
	ldr	__a3, |L..210|+48
	add	__v6, __v6, #1
	add	__ip, __v5, __a3
	stmia	__ip, {__a1-__a2}
	mov	__a2, __v4
	mov	__a1, __v3
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__divdf3|
	ldr	__a4, |L..210|+52
	cmp	__v6, #7
	add	__v5, __v5, __a4
	stmia	__v5, {__a1-__a2}
	ble	|L..17|
	mov	__v6, #0
|L..22|
	mov	__v4, __v6, asl #1
	orr	__a1, __v4, #1
	ldr	__v1, |L..210|+56
	mov	__v3, __v6, asl #3
	ldr	__v2, |L..210|+60
	add	__v5, __v3, __v1
	add	__v3, __v3, __v2
	bl	|__floatsidf|
	adr	__a3, |L..210|+64
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	bl	|sin|
	adr	__a3, |L..210|+72
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	mov	__v2, __a2
	mov	__v1, __a1
	add	__a1, __v4, #19
	bl	|__floatsidf|
	adr	__a3, |L..210|+64
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	bl	|cos|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__divdf3|
	mov	__a4, __a2
	mov	__a3, __a1
	stmia	__v3, {__a3-__a4}
	add	__v1, __v6, #18
	stmia	__v5, {__a3-__a4}
	mov	__v4, __v1, asl #1
	orr	__a1, __v4, #1
	ldr	__v3, |L..210|+56
	mov	__v1, __v1, asl #3
	ldr	__ip, |L..210|+80
	add	__v5, __v1, __v3
	add	__v1, __v1, __ip
	bl	|__floatsidf|
	adr	__a3, |L..210|+64
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	bl	|sin|
	adr	__a3, |L..210|+72
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	mov	__v3, __a2
	mov	__v2, __a1
	add	__a1, __v4, #19
	bl	|__floatsidf|
	adr	__a3, |L..210|+64
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	bl	|cos|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__divdf3|
	stmia	__v1, {__a1-__a2}
	add	__v6, __v6, #1
	cmp	__v6, #17
	stmia	__v5, {__a1-__a2}
	ble	|L..22|
	mov	__v6, #0
	ldr	__v5, |L..210|+60
|L..27|
	add	__v1, __v6, #18
	mov	__a1, __v1, asl #1
	add	__a1, __a1, #19
	add	__v1, __v5, __v1, asl #3
	bl	|__floatsidf|
	adr	__a3, |L..210|+64
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	bl	|cos|
	mov	__a4, __a2
	mov	__a3, __a1
	adr	__a1, |L..210|+72
	ldmia	__a1, {__a1-__a2}
	bl	|__divdf3|
	stmia	__v1, {__a1-__a2}
	add	__v2, __v6, #12
	mov	__a1, __v2, asl #1
	ldr	__lr, |L..210|+80
	add	__a1, __a1, #19
	add	__v2, __lr, __v2, asl #3
	bl	|__floatsidf|
	adr	__a3, |L..210|+64
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	bl	|cos|
	mov	__a4, __a2
	mov	__a3, __a1
	adr	__a1, |L..210|+72
	ldmia	__a1, {__a1-__a2}
	bl	|__divdf3|
	mov	__v4, __v6, asl #1
	stmia	__v2, {__a1-__a2}
	add	__a1, __v4, #13
	bl	|__floatsidf|
	adr	__a3, |L..210|+84
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	bl	|sin|
	adr	__a3, |L..210|+72
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	add	__v1, __v6, #24
	mov	__v3, __a2
	mov	__v2, __a1
	mov	__a1, __v1, asl #1
	add	__a1, __a1, #19
	bl	|__floatsidf|
	adr	__a3, |L..210|+64
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	bl	|cos|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__divdf3|
	add	__v1, __v5, __v1, asl #3
	stmia	__v1, {__a1-__a2}
	ldr	__a2, |L..210|+80
	adr	__a4, |L..210|+92
	ldmia	__a4, {__a4-__v1}
	add	__ip, __a2, __v6, asl #3
	stmia	__ip, {__a4-__v1}
	add	__a3, __v6, #30
	add	__a3, __v5, __a3, asl #3
	stmia	__a3, {__a4-__v1}
	orr	__a1, __v4, #1
	bl	|__floatsidf|
	adr	__a3, |L..210|+84
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	bl	|sin|
	adr	__a3, |L..210|+72
	ldmia	__a3, {__a3-__a4}
	add	__v3, __v6, #6
	bl	|__muldf3|
	mov	__v2, __a2
	mov	__v1, __a1
	mov	__a1, __v3, asl #1
	add	__a1, __a1, #19
	bl	|__floatsidf|
	adr	__a3, |L..210|+64
	ldmia	__a3, {__a3-__a4}
	add	__v6, __v6, #1
	bl	|__muldf3|
	bl	|cos|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__divdf3|
	ldr	__a3, |L..210|+80
	cmp	__v6, #5
	add	__v3, __a3, __v3, asl #3
	stmia	__v3, {__a1-__a2}
	ble	|L..27|
	mov	__v6, #0
|L..32|
	mov	__a1, __v6
	b	|L..209|
|L..211|
	ALIGN
|L..210|
	DCD	|gainpow2|
	DCD	|ispow|
	DCD &bfd00000, &0	; double -2.50000000000000000000e-1
	DCD &40000000, &0	; double 2.00000000000000000000e0
	DCD &3ff55555, &55555555	; double 1.33333333333333325932e0
	DCD	8206
	DCD	|Ci.6|
	DCD &3ff00000, &0	; double 1.00000000000000000000e0
	DCD	|aa_cs|
	DCD	|aa_ca|
	DCD	|win|
	DCD	|win|+288
	DCD &3fa65718, &4ae74487	; double 4.36332312998582369512e-2
	DCD &3fe00000, &0	; double 5.00000000000000000000e-1
	DCD	|win|+864
	DCD &3fc0c152, &382d7365	; double 1.30899693899574703915e-1
	DCD &0, &0	; double 0.00000000000000000000e0
|L..209|
	bl	|__floatsidf|
	ldr	__v2, |L..213|
	adr	__a3, |L..213|+4
	ldmia	__a3, {__a3-__a4}
	add	__v1, __v2, __v6, asl #3
	add	__v6, __v6, #1
	bl	|__muldf3|
	bl	|cos|
	cmp	__v6, #8
	stmia	__v1, {__a1-__a2}
	ble	|L..32|
	mov	__v6, #0
|L..37|
	mov	__a1, __v6, asl #1
	orr	__a1, __a1, #1
	bl	|__floatsidf|
	ldr	__v3, |L..213|+12
	adr	__a3, |L..213|+16
	ldmia	__a3, {__a3-__a4}
	add	__v1, __v3, __v6, asl #3
	bl	|__muldf3|
	bl	|cos|
	mov	__a4, __a2
	mov	__a3, __a1
	adr	__a1, |L..213|+24
	ldmia	__a1, {__a1-__a2}
	add	__v6, __v6, #1
	bl	|__divdf3|
	cmp	__v6, #8
	stmia	__v1, {__a1-__a2}
	ble	|L..37|
	mov	__v6, #0
|L..42|
	mov	__a1, __v6, asl #1
	orr	__a1, __a1, #1
	bl	|__floatsidf|
	ldr	__v4, |L..213|+32
	adr	__a3, |L..213|+36
	ldmia	__a3, {__a3-__a4}
	add	__v1, __v4, __v6, asl #3
	bl	|__muldf3|
	bl	|cos|
	mov	__a4, __a2
	mov	__a3, __a1
	adr	__a1, |L..213|+24
	ldmia	__a1, {__a1-__a2}
	add	__v6, __v6, #1
	bl	|__divdf3|
	cmp	__v6, #2
	stmia	__v1, {__a1-__a2}
	ble	|L..42|
	adr	__a1, |L..213|+44
	ldmia	__a1, {__a1-__a2}
	bl	|cos|
	ldr	__ip, |L..213|+52
	stmia	__ip, {__a1-__a2}
	adr	__a1, |L..213|+56
	ldmia	__a1, {__a1-__a2}
	mov	__v6, #0
	bl	|cos|
	ldr	__ip, |L..213|+64
	stmia	__ip, {__a1-__a2}
|L..47|
	mov	__v4, __v6, asl #1
	ldr	__ip, |L..213|+68
	orr	__a1, __v4, #1
	add	__v5, __ip, #576
	add	__v5, __v5, __v6, asl #3
	bl	|__floatsidf|
	adr	__a3, |L..213|+72
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	bl	|sin|
	mov	__lr, #0
	str	__lr, [__sp, #4]
	add	__a3, __v6, #1
	str	__a3, [__sp, #20]
	adr	__a3, |L..213|+24
	ldmia	__a3, {__a3-__a4}
	add	__v1, __v4, #7
	str	__v1, [__sp, #8]
	bl	|__muldf3|
	mov	__v3, __a2
	mov	__v2, __a1
	mov	__a1, __v1
	bl	|__floatsidf|
	adr	__a3, |L..213|+72
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	bl	|cos|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v3
	mov	__a1, __v2
	bl	|__divdf3|
	add	__v4, __v4, __v6
	mov	__v2, __v4, asl #4
	stmia	__v5, {__a1-__a2}
|L..51|
	ldr	__a4, [__sp, #4]
	ldr	__a1, [__sp, #8]
	ldr	__v3, |L..213|+80
	mov	__ip, __a4, asl #1
	mov	__v1, __a1
	mla	__a1, __ip, __a1, __v1
	add	__v1, __v2, __a4, asl #3
	add	__v1, __v1, __v3
	bl	|__floatsidf|
	ldr	__v4, [__sp, #4]
	adr	__a3, |L..213|+72
	ldmia	__a3, {__a3-__a4}
	add	__v4, __v4, #1
	str	__v4, [__sp, #4]
	bl	|__muldf3|
	bl	|cos|
	cmp	__v4, #5
	stmia	__v1, {__a1-__a2}
	ble	|L..51|
	ldr	__v6, [__sp, #20]
	cmp	__v6, #11
	ble	|L..47|
	mov	__ip, #0
	str	__ip, [__sp, #4]
	ldr	__v5, |L..213|+84
|L..57|
	ldr	__lr, [__sp, #4]
	mov	__v6, #0
	mov	__ip, __lr, asl #2
	ldr	__a3, [__v5, __ip]
	mov	__v1, __ip
	cmp	__v6, __a3
	bge	|L..59|
	ldr	__a1, |L..213|+88
	add	__ip, __lr, __lr, asl #3
	ldr	__a3, |L..213|+84
	mov	__a2, __ip, asl #5
	ldr	__a4, [__a3, __v1]
|L..61|
	add	__ip, __a2, __v6, asl #3
	add	__a3, __ip, __a1
	ldr	__v2, |L..213|+68
	add	__v6, __v6, #2
	add	__ip, __ip, __v2
	ldmia	__ip, {__v3-__v4}
	cmp	__v6, __a4
	stmia	__a3, {__v3-__v4}
	blt	|L..61|
|L..59|
	ldr	__v4, |L..213|+84
	ldr	__a3, [__v4, __v1]
	mov	__v6, #1
	cmp	__v6, __a3
	bge	|L..56|
	ldr	__lr, [__sp, #4]
	mov	__v2, __a3
	ldr	__v4, |L..213|+88
	add	__ip, __lr, __lr, asl #3
	mov	__v3, __ip, asl #5
|L..66|
	add	__v1, __v3, __v6, asl #3
	ldr	__a1, |L..213|+68
	add	__v6, __v6, #2
	add	__ip, __v1, __a1
	ldmia	__ip, {__a1-__a2}
	add	__v1, __v1, __v4
	bl	|__negdf2|
	cmp	__v6, __v2
	stmia	__v1, {__a1-__a2}
	blt	|L..66|
|L..56|
	ldr	__a2, [__sp, #4]
	add	__a2, __a2, #1
	cmp	__a2, #3
	str	__a2, [__sp, #4]
	ble	|L..57|
	mov	__v6, #0
|L..72|
	mov	__a1, __v6
	bl	|__floatsidf|
	adr	__a3, |L..213|+36
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	bl	|tan|
	mov	__v4, __a2
	mov	__v3, __a1
	adr	__a3, |L..213|+92
	ldmia	__a3, {__a3-__a4}
	bl	|__adddf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v4
	mov	__a1, __v3
	bl	|__divdf3|
	ldr	__a3, |L..213|+100
	mov	__v5, __v6, asl #3
	add	__ip, __v5, __a3
	stmia	__ip, {__a1-__a2}
	mov	__a4, #0
	str	__a4, [__sp, #4]
	adr	__a3, |L..213|+92
	ldmia	__a3, {__a3-__a4}
	mov	__a2, __v4
	mov	__a1, __v3
	bl	|__adddf3|
	mov	__a4, __a2
	mov	__a3, __a1
	adr	__a1, |L..213|+92
	ldmia	__a1, {__a1-__a2}
	bl	|__divdf3|
	ldr	__v1, |L..213|+104
	adr	__a3, |L..213|+108
	ldmia	__a3, {__a3-__a4}
	add	__ip, __v5, __v1
	stmia	__ip, {__a1-__a2}
	mov	__a2, __v4
	mov	__a1, __v3
	bl	|__muldf3|
	mov	__v2, __a2
	mov	__v1, __a1
	adr	__a3, |L..213|+92
	ldmia	__a3, {__a3-__a4}
	mov	__a2, __v4
	mov	__a1, __v3
	bl	|__adddf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__divdf3|
	ldr	__v2, |L..213|+116
	add	__ip, __v5, __v2
	stmia	__ip, {__a1-__a2}
	adr	__a3, |L..213|+92
	ldmia	__a3, {__a3-__a4}
	add	__ip, __v6, #1
	str	__ip, [__sp, #20]
	mov	__a2, __v4
	mov	__a1, __v3
	str	__v5, [__sp, #24]
	bl	|__adddf3|
	mov	__a4, __a2
	mov	__a3, __a1
	adr	__a1, |L..213|+108
	ldmia	__a1, {__a1-__a2}
	bl	|__divdf3|
	ldr	__lr, |L..213|+120
	b	|L..212|
|L..214|
	ALIGN
|L..213|
	DCD	|COS9|
	DCD &3fc65718, &4ae74487	; double 1.74532925199432947805e-1
	DCD	|tfcos36|
	DCD &3fb65718, &4ae74487	; double 8.72664625997164739024e-2
	DCD &3fe00000, &0	; double 5.00000000000000000000e-1
	DCD	|tfcos12|
	DCD &3fd0c152, &382d7365	; double 2.61799387799149407829e-1
	DCD &3fe0c152, &382d7365	; double 5.23598775598298815659e-1
	DCD	|COS6_1|
	DCD &3ff0c152, &382d7365	; double 1.04719755119659763132e0
	DCD	|COS6_2|
	DCD	|win|
	DCD &3fc0c152, &382d7365	; double 1.30899693899574703915e-1
	DCD	|COS1|
	DCD	|len.7|
	DCD	|win1|
	DCD &3ff00000, &0	; double 1.00000000000000000000e0
	DCD	|tan1_1|
	DCD	|tan2_1|
	DCD &3ff6a09e, &667f3bcd	; double 1.41421356237309514547e0
	DCD	|tan1_2|
	DCD	|tan2_2|
|L..212|
	add	__v5, __v5, __lr
	stmia	__v5, {__a1-__a2}
|L..76|
	ldr	__a1, [__sp, #4]
	bl	|__floatsidf|
	adr	__a3, |L..215|
	ldmia	__a3, {__a3-__a4}
	mov	__v4, __a4
	mov	__v3, __a3
	bl	|__adddf3|
	add	__v1, __sp, #16
	stmda	__v1, {__v3-__v4}
	adr	__a3, |L..215|+8
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	adr	__a1, |L..215|+16
	ldmia	__a1, {__a1-__a2}
	bl	|pow|
	cmp	__v6, #0
	mov	__v2, __a2
	mov	__v1, __a1
	ble	|L..77|
	tst	__v6, #1
	beq	|L..78|
	mov	__a1, __v6
	bl	|__floatsidf|
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__adddf3|
	adr	__a3, |L..215|+24
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|pow|
	add	__v2, __sp, #16
	stmda	__v2, {__a1-__a2}
	b	|L..77|
|L..216|
	ALIGN
|L..215|
	DCD &3ff00000, &0	; double 1.00000000000000000000e0
	DCD &bfd00000, &0	; double -2.50000000000000000000e-1
	DCD &40000000, &0	; double 2.00000000000000000000e0
	DCD &3fe00000, &0	; double 5.00000000000000000000e-1
|L..78|
	mov	__a1, __v6
	bl	|__floatsidf|
	adr	__a3, |L..218|
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|pow|
	mov	__v4, __a2
	mov	__v3, __a1
|L..77|
	add	__ip, __sp, #16
	ldmda	__ip, {__a1-__a2}
	ldr	__lr, [__sp, #24]
	ldr	__a3, [__sp, #4]
	ldr	__a4, |L..218|+8
	add	__v1, __lr, __a3, asl #7
	add	__ip, __v1, __a4
	add	__a4, __sp, #16
	ldmda	__a4, {__a3-__a4}
	stmia	__ip, {__a3-__a4}
	ldr	__v2, |L..218|+12
	adr	__a3, |L..218|+16
	ldmia	__a3, {__a3-__a4}
	add	__ip, __v1, __v2
	stmia	__ip, {__v3-__v4}
	bl	|__muldf3|
	ldr	__lr, |L..218|+24
	adr	__a3, |L..218|+16
	ldmia	__a3, {__a3-__a4}
	add	__ip, __v1, __lr
	stmia	__ip, {__a1-__a2}
	mov	__a2, __v4
	mov	__a1, __v3
	bl	|__muldf3|
	ldr	__a3, [__sp, #4]
	ldr	__a4, |L..218|+28
	add	__a3, __a3, #1
	cmp	__a3, #1
	str	__a3, [__sp, #4]
	add	__v1, __v1, __a4
	stmia	__v1, {__a1-__a2}
	ble	|L..76|
	ldr	__v6, [__sp, #20]
	cmp	__v6, #15
	ble	|L..72|
	mov	__v1, #0
	str	__v1, [__sp, #4]
	ldr	__v5, |L..218|+32
|L..85|
	ldr	__v2, [__sp, #4]
	mov	__v6, #0
	ldr	__v3, |L..218|+36
	mov	__a1, __v6
	ldr	__v4, |L..218|+40
	add	__ip, __v2, __v2, asl #3
	add	__a3, __v2, __ip, asl #1
	add	__a3, __v3, __a3, asl #5
	mov	__a2, __a3
	add	__a4, __v4, __ip, asl #4
	mov	__ip, __v2, asl #1
	mov	__v3, __ip
	mov	__v1, __v2, asl #2
	add	__ip, __ip, __v2
	ldr	__v2, |L..218|+44
	add	__lr, __a4, #46
	str	__a3, [__v2, __ip, asl #2]
|L..89|
	ldr	__ip, [__lr, #0]	; movhi
	mov	__ip, __ip, asl #16
	mov	__ip, __ip, asr #17
	str	__ip, [__a2], #4
	str	__v6, [__a2], #4
	mov	__v4, #3
	str	__v4, [__a2], #4
	str	__a1, [__a2], #4
	add	__a1, __a1, #1
	ldr	__ip, [__lr], #2	; movhi
	cmp	__a1, #7
	mov	__ip, __ip, asl #16
	add	__v6, __v6, __ip, asr #16
	ble	|L..89|
	add	__lr, __a4, #124
	mov	__a1, __v4
	add	__v4, __a4, #46
	add	__v2, __a4, #118
|L..94|
	ldr	__ip, [__lr], #2	; movhi
	mov	__a3, #0
	mov	__ip, __ip, asl #16
	mov	__a4, __ip, asr #17
|L..98|
	str	__a4, [__a2], #4
	add	__ip, __v6, __a3
	str	__ip, [__a2], #4
	str	__a3, [__a2], #4
	add	__a3, __a3, #1
	cmp	__a3, #2
	str	__a1, [__a2], #4
	ble	|L..98|
	add	__ip, __a4, __a4, asl #1
	add	__v6, __v6, __ip, asl #1
	add	__a1, __a1, #1
	cmp	__a1, #12
	ble	|L..94|
	ldr	__ip, [__sp, #4]
	ldr	__a1, |L..218|+48
	ldr	__a4, |L..218|+52
	add	__a3, __v3, __ip
	mov	__a3, __a3, asl #2
	str	__a2, [__v5, __a3]
	mov	__v6, #0
	ldr	__lr, [__sp, #4]
	add	__ip, __v1, __ip
	rsb	__ip, __lr, __ip, asl #3
	add	__ip, __a1, __ip, asl #4
	mov	__a2, __ip
	mov	__lr, __v2
	mov	__a1, __v6
	str	__ip, [__a3, __a4]
|L..104|
	ldr	__ip, [__lr], #2	; movhi
	mov	__a3, #0
	mov	__ip, __ip, asl #16
	mov	__a4, __ip, asr #17
|L..108|
	str	__a4, [__a2], #4
	add	__ip, __v6, __a3
	str	__ip, [__a2], #4
	str	__a3, [__a2], #4
	add	__a3, __a3, #1
	cmp	__a3, #2
	str	__a1, [__a2], #4
	ble	|L..108|
	add	__ip, __a4, __a4, asl #1
	add	__v6, __v6, __ip, asl #1
	add	__a1, __a1, #1
	cmp	__a1, #12
	ble	|L..104|
	ldr	__v2, [__sp, #4]
	ldr	__lr, |L..218|+56
	mov	__a1, #0
	ldr	__a4, |L..218|+60
	add	__a3, __v3, __v2
	mov	__a3, __a3, asl #2
	add	__ip, __v1, __v2
	add	__ip, __v2, __ip, asl #1
	add	__ip, __lr, __ip, asl #4
	ldr	__v3, |L..218|+64
	mov	__lr, __v4
	str	__a2, [__v3, __a3]
	mov	__a2, __ip
	str	__ip, [__a3, __a4]
|L..114|
	ldr	__ip, [__lr], #2	; movhi
	mov	__ip, __ip, asl #16
	mov	__ip, __ip, asr #17
	str	__ip, [__a2], #4
	str	__a1, [__a2], #4
	add	__a1, __a1, #1
	cmp	__a1, #21
	ble	|L..114|
	ldr	__v1, [__sp, #4]
	ldr	__v2, |L..218|+68
	add	__ip, __v1, __v1, asl #1
	add	__v1, __v1, #1
	str	__v1, [__sp, #4]
	cmp	__v1, #8
	str	__a2, [__v2, __ip, asl #2]
	ble	|L..85|
	ldr	__v3, |L..218|+72
	ldr	__v2, |L..218|+40
	mov	__v4, #0
	str	__v4, [__sp, #4]
	ldr	__v1, |L..218|+76
|L..120|
	ldr	__lr, [__sp, #4]
	mov	__v6, #0
	add	__ip, __lr, __lr, asl #1
	rsb	__ip, __lr, __ip, asl #3
	mov	__a1, __ip, asl #2
	mov	__a4, __lr, asl #3
	add	__ip, __a4, __lr
	mov	__a2, __ip, asl #4
|L..124|
	add	__ip, __a2, __v6, asl #1
	ldr	__a3, [__v2, __ip]	; movhi
	mov	__a3, __a3, asl #16
	mov	__a3, __a3, asr #16
	add	__a3, __a3, #7
	smull	__v4, __ip, __v1, __a3
	mov	__a3, __a3, asr #31
	rsb	__a3, __a3, __ip, asr #2
	ldr	__ip, [__sp, #0]
	add	__a3, __a3, #1
	cmp	__a3, __ip
	add	__ip, __a1, __v6, asl #2
	str	__a3, [__v3, __ip]
	ble	|L..123|
	ldr	__a3, [__sp, #0]
	ldr	__lr, |L..218|+72
	str	__a3, [__lr, __ip]
|L..123|
	add	__v6, __v6, #1
	cmp	__v6, #22
	ble	|L..124|
	ldr	__v4, [__sp, #4]
	ldr	__lr, |L..218|+80
	mov	__v6, #0
	ldr	__a1, |L..218|+84
	rsb	__ip, __v4, __a4
	mov	__a2, __ip, asl #3
	add	__ip, __a4, __v4
	mov	__a4, __ip, asl #4
|L..130|
	add	__ip, __a4, __v6, asl #1
	ldr	__a3, [__a1, __ip]	; movhi
	mov	__a3, __a3, asl #16
	mov	__a3, __a3, asr #16
	sub	__a3, __a3, #1
	smull	__v4, __ip, __v1, __a3
	mov	__a3, __a3, asr #31
	rsb	__a3, __a3, __ip, asr #2
	ldr	__ip, [__sp, #0]
	add	__a3, __a3, #1
	cmp	__a3, __ip
	add	__ip, __a2, __v6, asl #2
	str	__a3, [__lr, __ip]
	ble	|L..129|
	ldr	__v4, [__sp, #0]
	ldr	__a3, |L..218|+80
	str	__v4, [__a3, __ip]
|L..129|
	add	__v6, __v6, #1
	cmp	__v6, #13
	ble	|L..130|
	ldr	__ip, [__sp, #4]
	add	__ip, __ip, #1
	cmp	__ip, #8
	str	__ip, [__sp, #4]
	ble	|L..120|
	mov	__v6, #0
	ldr	__v1, |L..218|+88
|L..137|
	mov	__lr, #0
	add	__ip, __v6, __v6, asl #3
	mov	__a1, __ip, asl #2
	str	__lr, [__sp, #4]
|L..141|
	ldr	__a2, [__sp, #4]
	mov	__lr, #0
	ldr	__a3, [__sp, #4]
	add	__ip, __a2, __a2, asl #1
	mov	__a2, __ip, asl #1
	orr	__a4, __v6, __a3, asl #3
|L..145|
	add	__a3, __lr, __a2
	orr	__ip, __a4, __lr, asl #6
	add	__lr, __lr, #1
	b	|L..217|
|L..219|
	ALIGN
|L..218|
	DCD &3fe00000, &0	; double 5.00000000000000000000e-1
	DCD	|pow1_1|
	DCD	|pow2_1|
	DCD &3ff6a09e, &667f3bcd	; double 1.41421356237309514547e0
	DCD	|pow1_2|
	DCD	|pow2_2|
	DCD	|mapend|
	DCD	|mapbuf0|
	DCD	|bandInfo|
	DCD	|map|
	DCD	|mapbuf1|
	DCD	|map|+4
	DCD	|mapbuf2|
	DCD	|map|+8
	DCD	|mapend|+4
	DCD	|mapend|+8
	DCD	|longLimit|
	DCD	954437177
	DCD	|shortLimit|
	DCD	|bandInfo|+90
	DCD	|i_slen2|
|L..217|
	cmp	__lr, #5
	add	__a3, __a3, __a1
	orr	__ip, __ip, #12288
	str	__ip, [__v1, __a3, asl #2]
	ble	|L..145|
	ldr	__a4, [__sp, #4]
	add	__a4, __a4, #1
	cmp	__a4, #5
	str	__a4, [__sp, #4]
	ble	|L..141|
	add	__v6, __v6, #1
	cmp	__v6, #4
	ble	|L..137|
	mov	__v6, #0
	ldr	__v1, |L..220|
|L..152|
	mov	__v2, #0
	mov	__a1, __v6, asl #4
	str	__v2, [__sp, #4]
|L..156|
	ldr	__v3, [__sp, #4]
	mov	__lr, #0
	mov	__a2, __v3, asl #2
	orr	__a4, __v6, __v3, asl #3
|L..160|
	add	__ip, __lr, __a2
	orr	__a3, __a4, __lr, asl #6
	add	__lr, __lr, #1
	cmp	__lr, #3
	add	__ip, __ip, __a1
	add	__ip, __ip, #180
	orr	__a3, __a3, #16384
	str	__a3, [__v1, __ip, asl #2]
	ble	|L..160|
	ldr	__v4, [__sp, #4]
	add	__v4, __v4, #1
	cmp	__v4, #3
	str	__v4, [__sp, #4]
	ble	|L..156|
	add	__v6, __v6, #1
	cmp	__v6, #3
	ble	|L..152|
	ldr	__v1, |L..220|
	mov	__v6, #0
	ldr	__lr, |L..220|+4
|L..167|
	mov	__ip, #0
	add	__a1, __v6, __v6, asl #1
	str	__ip, [__sp, #4]
|L..171|
	ldr	__a3, [__sp, #4]
	add	__a2, __a3, __a1
	orr	__a4, __v6, __a3, asl #3
	add	__a3, __a3, #1
	cmp	__a3, #2
	str	__a3, [__sp, #4]
	add	__a3, __a2, #244
	orr	__ip, __a4, #20480
	add	__a2, __a2, #500
	str	__ip, [__v1, __a3, asl #2]
	orr	__a4, __a4, #40960
	str	__a4, [__lr, __a2, asl #2]
	ble	|L..171|
	add	__v6, __v6, #1
	cmp	__v6, #3
	ble	|L..167|
	mov	__v6, #0
	ldr	__v4, |L..220|+4
|L..177|
	mov	__a4, #0
	add	__ip, __v6, __v6, asl #2
	mov	__v3, __ip, asl #4
	str	__a4, [__sp, #4]
|L..181|
	ldr	__v2, [__sp, #4]
	mov	__lr, #0
	mov	__v1, __v2, asl #4
	orr	__v2, __v6, __v2, asl #3
|L..185|
	mov	__a4, #0
	mov	__a1, __lr, asl #2
	orr	__a2, __v2, __lr, asl #6
|L..189|
	add	__ip, __a4, __a1
	orr	__a3, __a2, __a4, asl #9
	add	__a4, __a4, #1
	cmp	__a4, #3
	add	__ip, __ip, __v1
	add	__ip, __ip, __v3
	str	__a3, [__v4, __ip, asl #2]
	ble	|L..189|
	add	__lr, __lr, #1
	cmp	__lr, #3
	ble	|L..185|
	ldr	__ip, [__sp, #4]
	add	__ip, __ip, #1
	cmp	__ip, #4
	str	__ip, [__sp, #4]
	ble	|L..181|
	add	__v6, __v6, #1
	cmp	__v6, #4
	ble	|L..177|
	mov	__v6, #0
	ldr	__v2, |L..220|+4
|L..197|
	mov	__lr, #0
	add	__a1, __v6, #1
	add	__ip, __v6, __v6, asl #2
	str	__lr, [__sp, #4]
	mov	__v1, __ip, asl #2
	str	__a1, [__sp, #20]
|L..201|
	ldr	__a3, [__sp, #4]
	mov	__lr, #0
	add	__a2, __a3, #1
	mov	__a4, __a3, asl #2
	orr	__a1, __v6, __a3, asl #3
|L..205|
	add	__ip, __lr, __a4
	orr	__a3, __a1, __lr, asl #6
	add	__lr, __lr, #1
	cmp	__lr, #3
	add	__ip, __ip, __v1
	add	__ip, __ip, #400
	orr	__a3, __a3, #4096
	str	__a3, [__v2, __ip, asl #2]
	ble	|L..205|
	str	__a2, [__sp, #4]
	cmp	__a2, #4
	ble	|L..201|
	ldr	__v6, [__sp, #20]
	cmp	__v6, #4
	ble	|L..197|
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..221|
	ALIGN
|L..220|
	DCD	|i_slen2|
	DCD	|n_slen2|
	ALIGN
|LC..0|
	DCB &62, &69, &67, &5f
	DCB &76, &61, &6c, &75
	DCB &65, &73, &20, &74
	DCB &6f, &6f, &20, &6c
	DCB &61, &72, &67, &65
	DCB &21, &20, &25, &69
	DCB &0a, &00
	ALIGN
|LC..1|
	DCB &42, &6c, &6f, &63
	DCB &6b, &74, &79, &70
	DCB &65, &20, &3d, &3d
	DCB &20, &30, &20, &61
	DCB &6e, &64, &20, &77
	DCB &69, &6e, &64, &6f
	DCB &77, &2d, &73, &77
	DCB &69, &74, &63, &68
	DCB &69, &6e, &67, &20
	DCB &3d, &3d, &20, &31
	DCB &20, &6e, &6f, &74
	DCB &20, &61, &6c, &6c
	DCB &6f, &77, &65, &64
	DCB &2e, &0a, &00
	ALIGN
|III_get_side_info_1|
	KEEP |III_get_side_info_1|
	; args = 4, pretend = 0, frame = 24, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	bllt	|__rt_stkovf_split_small|
	sub	__sp, __sp, #24
	stmia	__sp, {__a1, __a2, __a3}	; phole stm
	ldr	__ip, [__fp, #4]
	mov	__a1, #9
	str	__a4, [__sp, #12]
	cmp	__ip, #3
	moveq	__ip, #4
	movne	__ip, #0
	str	__ip, [__sp, #16]
	bl	|getbits|
	ldr	__a2, [__sp, #4]
	ldr	__a3, [__sp, #0]
	cmp	__a2, #1
	str	__a1, [__a3, #0]
	bne	|L..225|
	mov	__a1, #5
	bl	|getbits_fast|
	ldr	__a4, [__sp, #0]
	str	__a1, [__a4, #4]
	b	|L..226|
|L..225|
	mov	__a1, #3
	bl	|getbits_fast|
	ldr	__ip, [__sp, #0]
	str	__a1, [__ip, #4]
|L..226|
	ldr	__lr, [__sp, #4]
	mov	__v4, #0
	cmp	__v4, __lr
	bge	|L..228|
	ldr	__a1, [__sp, #0]
	add	__v2, __a1, #8
|L..230|
	mov	__a1, #4
	add	__v1, __v4, __v4, asl #1
	add	__v1, __v4, __v1, asl #2
	mov	__v1, __v1, asl __a1
	mvn	__ip, #0
	str	__ip, [__v2, __v1]
	bl	|getbits_fast|
	ldr	__a2, [__sp, #4]
	add	__v4, __v4, #1
	ldr	__a3, [__sp, #0]
	cmp	__v4, __a2
	add	__ip, __a3, #112
	str	__a1, [__ip, __v1]
	blt	|L..230|
|L..228|
	mov	__v6, #0
|L..235|
	mov	__v4, #0
	ldr	__a4, [__sp, #4]
	add	__ip, __v6, #1
	str	__ip, [__sp, #20]
	cmp	__v4, __a4
	bge	|L..234|
|L..239|
	mov	__a1, #12
	add	__a3, __v4, __v4, asl #1
	add	__a3, __v4, __a3, asl #2
	mov	__a3, __a3, asl #4
	add	__a3, __a3, #8
	add	__ip, __v6, __v6, asl #1
	ldr	__lr, [__sp, #0]
	add	__ip, __v6, __ip, asl #2
	add	__a3, __lr, __a3
	add	__v3, __a3, __ip, asl #3
	bl	|getbits|
	str	__a1, [__v3, #4]
	mov	__a1, #9
	bl	|getbits_fast|
	mov	__a3, __a1
	cmp	__a3, #288
	str	__a3, [__v3, #8]
	bls	|L..240|
	ldr	__ip, |L..262|
	ldr	__a2, |L..262|+4
	ldr	__a1, [__ip, #0]
	bl	|fprintf|
	mov	__ip, #288
	str	__ip, [__v3, #8]
|L..240|
	mov	__a1, #8
	bl	|getbits_fast|
	ldr	__ip, |L..262|+8
	ldr	__a2, [__sp, #8]
	ldr	__a3, [__sp, #16]
	cmp	__a2, #0
	add	__ip, __ip, __a3, asl #3
	sub	__ip, __ip, __a1, asl #3
	str	__ip, [__v3, #100]
	addne	__ip, __ip, #16
	strne	__ip, [__v3, #100]
|L..241|
	mov	__a1, #4
	bl	|getbits_fast|
	str	__a1, [__v3, #12]
	ldr	__v2, |L..262|+12
	ldr	__v1, |L..262|+16
	ldr	__a2, [__v2, #0]
	ldr	__a3, [__v1, #0]
	add	__a4, __a2, #1
	ldrb	__ip, [__a3, #0]	; zero_extendqisi2
	add	__a3, __a3, __a4, asr #3
	str	__a3, [__v1, #0]
	and	__a4, __a4, #7
	str	__a4, [__v2, #0]
	mov	__ip, __ip, asl __a2
	and	__ip, __ip, #255
	movs	__ip, __ip, lsr #7
	beq	|L..242|
	mov	__a1, #2
	bl	|getbits_fast|
	str	__a1, [__v3, #16]
	mov	__a1, #5
	add	__v5, __v4, #1
	ldr	__a2, [__v2, #0]
	add	__v4, __v3, #88
	ldr	__a3, [__v1, #0]
	add	__a4, __a2, #1
	ldrb	__ip, [__a3, #0]	; zero_extendqisi2
	add	__a3, __a3, __a4, asr #3
	str	__a3, [__v1, #0]
	and	__a4, __a4, #7
	str	__a4, [__v2, #0]
	mov	__ip, __ip, asl __a2
	and	__ip, __ip, #255
	mov	__ip, __ip, lsr #7
	str	__ip, [__v3, #20]
	bl	|getbits_fast|
	str	__a1, [__v3, #24]
	mov	__a1, #5
	bl	|getbits_fast|
	mov	__ip, #0
	str	__a1, [__v3, #28]
	mov	__v1, __ip
	str	__ip, [__v3, #32]
|L..248|
	mov	__a1, #3
	bl	|getbits_fast|
	ldr	__ip, [__v3, #100]
	add	__ip, __ip, __a1, asl #6
	str	__ip, [__v4, __v1, asl #2]
	add	__v1, __v1, #1
	cmp	__v1, #2
	ble	|L..248|
	ldr	__ip, [__v3, #16]
	cmp	__ip, #0
	bne	|L..250|
	ldr	__ip, |L..262|
	ldr	__a2, |L..262|+20
	ldr	__a1, [__ip, #0]
	bl	|fprintf|
	mov	__a1, #1
	bl	|exit|
|L..250|
	mov	__ip, #18
	str	__ip, [__v3, #68]
	mov	__a3, #288
	str	__a3, [__v3, #72]
	b	|L..251|
|L..242|
	mov	__v1, __ip
	add	__v5, __v4, #1
	ldr	__a4, [__sp, #12]
	add	__v2, __v3, #24
	mov	__v4, __a4, asl #3
|L..255|
	mov	__a1, #5
	bl	|getbits_fast|
	str	__a1, [__v2, __v1, asl #2]
	add	__v1, __v1, #1
	cmp	__v1, #2
	ble	|L..255|
	mov	__a1, #4
	bl	|getbits_fast|
	mov	__v1, __a1
	mov	__a1, #3
	bl	|getbits_fast|
	mov	__a2, #0
	add	__ip, __v1, #1
	str	__a2, [__v3, #16]
	add	__a1, __a1, __v1
	ldr	__lr, [__sp, #12]
	add	__a1, __a1, #2
	str	__a2, [__v3, #20]
	add	__a3, __v4, __lr
	mov	__a3, __a3, asl #4
	ldr	__lr, |L..262|+24
	add	__ip, __a3, __ip, asl #1
	ldr	__a4, [__lr, __ip]	; movhi
	add	__a3, __a3, __a1, asl #1
	ldr	__ip, [__lr, __a3]	; movhi
	mov	__a4, __a4, asl #16
	mov	__a4, __a4, asr #17
	mov	__ip, __ip, asl #16
	str	__a4, [__v3, #68]
	mov	__ip, __ip, asr #17
	str	__ip, [__v3, #72]
|L..251|
	ldr	__a1, |L..262|+12
	ldr	__a2, [__sp, #4]
	ldr	__ip, |L..262|+16
	ldr	__lr, |L..262|+16
	ldr	__a4, [__a1, #0]
	mov	__v4, __v5
	ldr	__a1, [__ip, #0]
	cmp	__v4, __a2
	ldr	__a2, |L..262|+12
	add	__a3, __a4, #1
	mov	__v1, __a3, asr #3
	ldrb	__ip, [__a1, #0]	; zero_extendqisi2
	add	__v2, __a1, __v1
	str	__v2, [__lr, #0]
	and	__a3, __a3, #7
	str	__a3, [__a2, #0]
	mov	__ip, __ip, asl __a4
	and	__ip, __ip, #255
	mov	__ip, __ip, lsr #7
	add	__a4, __a3, #1
	mov	__lr, __a4, asr #3
	str	__ip, [__v3, #76]
	add	__a2, __v2, __lr
	ldrb	__ip, [__a1, __v1]	; zero_extendqisi2
	and	__a4, __a4, #7
	ldr	__a1, |L..262|+16
	mov	__ip, __ip, asl __a3
	str	__a2, [__a1, #0]
	and	__ip, __ip, #255
	ldr	__a1, |L..262|+12
	mov	__ip, __ip, lsr #7
	str	__a4, [__a1, #0]
	add	__a3, __a4, #1
	str	__ip, [__v3, #80]
	add	__a2, __a2, __a3, lsr #3
	ldrb	__ip, [__v2, __lr]	; zero_extendqisi2
	and	__a3, __a3, #7
	ldr	__lr, |L..262|+16
	mov	__ip, __ip, asl __a4
	str	__a2, [__lr, #0]
	and	__ip, __ip, #255
	str	__a3, [__a1, #0]
	mov	__ip, __ip, lsr #7
	str	__ip, [__v3, #84]
	blt	|L..239|
|L..234|
	ldr	__v6, [__sp, #20]
	cmp	__v6, #1
	ble	|L..235|
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..263|
	ALIGN
|L..262|
	DCD	|__stderr|
	DCD	|LC..0|
	DCD	|gainpow2|+2048
	DCD	|bitindex|
	DCD	|wordpointer|
	DCD	|LC..1|
	DCD	|bandInfo|
	ALIGN
|III_get_side_info_2|
	KEEP |III_get_side_info_2|
	; args = 4, pretend = 0, frame = 16, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	bllt	|__rt_stkovf_split_small|
	sub	__sp, __sp, #16
	stmia	__sp, {__a1, __a2}	; phole stm
	mov	__a1, #8
	ldr	__ip, [__fp, #4]
	mov	__v6, __a4
	str	__a3, [__sp, #8]
	cmp	__ip, #3
	moveq	__ip, #4
	movne	__ip, #0
	str	__ip, [__sp, #12]
	bl	|getbits|
	ldr	__a2, [__sp, #4]
	ldr	__a3, [__sp, #0]
	cmp	__a2, #1
	str	__a1, [__a3, #0]
	bne	|L..267|
	ldr	__lr, |L..300|
	ldr	__a2, |L..300|+4
	ldr	__a1, [__lr, #0]
	ldr	__a3, [__a2, #0]
	add	__a4, __a1, #1
	ldrb	__ip, [__a3, #0]	; zero_extendqisi2
	add	__a3, __a3, __a4, asr #3
	str	__a3, [__a2, #0]
	and	__a4, __a4, #7
	str	__a4, [__lr, #0]
	ldr	__a4, [__sp, #0]
	mov	__ip, __ip, asl __a1
	and	__ip, __ip, #255
	mov	__ip, __ip, lsr #7
	str	__ip, [__a4, #4]
	b	|L..269|
|L..267|
	mov	__a1, #2
	bl	|getbits_fast|
	ldr	__v1, [__sp, #0]
	str	__a1, [__v1, #4]
|L..269|
	ldr	__ip, [__sp, #4]
	mov	__v5, #0
	cmp	__v5, __ip
	bge	|L..271|
|L..273|
	mov	__a1, #12
	add	__ip, __v5, __v5, asl #1
	add	__ip, __v5, __ip, asl #2
	mov	__ip, __ip, asl #4
	ldr	__lr, [__sp, #0]
	add	__ip, __ip, #8
	add	__v2, __lr, __ip
	bl	|getbits|
	str	__a1, [__v2, #4]
	mov	__a1, #9
	bl	|getbits_fast|
	mov	__a3, __a1
	cmp	__a3, #288
	str	__a3, [__v2, #8]
	bls	|L..274|
	ldr	__ip, |L..300|+8
	ldr	__a2, |L..300|+12
	ldr	__a1, [__ip, #0]
	bl	|fprintf|
	mov	__ip, #288
	str	__ip, [__v2, #8]
|L..274|
	mov	__a1, #8
	bl	|getbits_fast|
	ldr	__ip, |L..300|+16
	ldr	__a2, [__sp, #8]
	ldr	__a3, [__sp, #12]
	cmp	__a2, #0
	add	__ip, __ip, __a3, asl #3
	sub	__ip, __ip, __a1, asl #3
	str	__ip, [__v2, #100]
	addne	__ip, __ip, #16
	strne	__ip, [__v2, #100]
|L..275|
	mov	__a1, #9
	bl	|getbits|
	str	__a1, [__v2, #12]
	ldr	__v3, |L..300|
	ldr	__v1, |L..300|+4
	ldr	__a2, [__v3, #0]
	ldr	__ip, [__v1, #0]
	add	__a3, __a2, #1
	ldrb	__a4, [__ip, #0]	; zero_extendqisi2
	add	__ip, __ip, __a3, asr #3
	str	__ip, [__v1, #0]
	and	__a3, __a3, #7
	str	__a3, [__v3, #0]
	mov	__a4, __a4, asl __a2
	and	__a4, __a4, #255
	movs	__a4, __a4, lsr #7
	beq	|L..276|
	mov	__a1, #2
	bl	|getbits_fast|
	str	__a1, [__v2, #16]
	mov	__a1, #5
	add	__v4, __v2, #88
	ldr	__a2, [__v3, #0]
	add	__v5, __v5, #1
	ldr	__a3, [__v1, #0]
	add	__a4, __a2, #1
	ldrb	__ip, [__a3, #0]	; zero_extendqisi2
	add	__a3, __a3, __a4, asr #3
	str	__a3, [__v1, #0]
	and	__a4, __a4, #7
	str	__a4, [__v3, #0]
	mov	__ip, __ip, asl __a2
	and	__ip, __ip, #255
	mov	__ip, __ip, lsr #7
	str	__ip, [__v2, #20]
	bl	|getbits_fast|
	str	__a1, [__v2, #24]
	mov	__a1, #5
	bl	|getbits_fast|
	mov	__ip, #0
	str	__a1, [__v2, #28]
	mov	__v1, __ip
	str	__ip, [__v2, #32]
|L..282|
	mov	__a1, #3
	bl	|getbits_fast|
	ldr	__ip, [__v2, #100]
	add	__ip, __ip, __a1, asl #6
	str	__ip, [__v4, __v1, asl #2]
	add	__v1, __v1, #1
	cmp	__v1, #2
	ble	|L..282|
	ldr	__ip, [__v2, #16]
	cmp	__ip, #0
	bne	|L..284|
	ldr	__ip, |L..300|+8
	ldr	__a2, |L..300|+20
	ldr	__a1, [__ip, #0]
	bl	|fprintf|
	mov	__a1, #1
	bl	|exit|
|L..284|
	cmp	__ip, #2
	moveq	__ip, #18
	beq	|L..298|
|L..285|
	cmp	__v6, #8
	mov	__ip, #27
	moveq	__ip, #54
|L..287|
|L..298|
	str	__ip, [__v2, #68]
	mov	__ip, #288
	b	|L..299|
|L..276|
	mov	__v1, __a4
	add	__v3, __v2, #24
	mov	__v4, __v6, asl #3
	add	__v5, __v5, #1
|L..293|
	mov	__a1, #5
	bl	|getbits_fast|
	str	__a1, [__v3, __v1, asl #2]
	add	__v1, __v1, #1
	cmp	__v1, #2
	ble	|L..293|
	mov	__a1, #4
	bl	|getbits_fast|
	mov	__v1, __a1
	mov	__a1, #3
	bl	|getbits_fast|
	mov	__a2, #0
	add	__ip, __v1, #1
	add	__a3, __v4, __v6
	mov	__a3, __a3, asl #4
	str	__a2, [__v2, #16]
	add	__ip, __a3, __ip, asl #1
	ldr	__lr, |L..300|+24
	add	__a1, __a1, __v1
	str	__a2, [__v2, #20]
	add	__a1, __a1, #2
	ldr	__a4, [__lr, __ip]	; movhi
	add	__a3, __a3, __a1, asl #1
	ldr	__ip, [__lr, __a3]	; movhi
	mov	__a4, __a4, asl #16
	mov	__a4, __a4, asr #17
	mov	__ip, __ip, asl #16
	str	__a4, [__v2, #68]
	mov	__ip, __ip, asr #17
|L..299|
	str	__ip, [__v2, #72]
	ldr	__a1, |L..300|
	ldr	__a2, [__sp, #4]
	ldr	__a4, |L..300|+4
	ldr	__v1, |L..300|+4
	ldr	__a3, [__a1, #0]
	cmp	__v5, __a2
	ldr	__a1, [__a4, #0]
	add	__a2, __a3, #1
	mov	__lr, __a2, asr #3
	ldrb	__ip, [__a1, #0]	; zero_extendqisi2
	add	__a4, __a1, __lr
	str	__a4, [__v1, #0]
	and	__a2, __a2, #7
	ldr	__v1, |L..300|
	mov	__ip, __ip, asl __a3
	and	__ip, __ip, #255
	mov	__ip, __ip, lsr #7
	str	__a2, [__v1, #0]
	add	__a3, __a2, #1
	str	__ip, [__v2, #80]
	add	__a4, __a4, __a3, lsr #3
	ldrb	__ip, [__a1, __lr]	; zero_extendqisi2
	and	__a3, __a3, #7
	ldr	__lr, |L..300|+4
	mov	__ip, __ip, asl __a2
	str	__a4, [__lr, #0]
	and	__ip, __ip, #255
	str	__a3, [__v1, #0]
	mov	__ip, __ip, lsr #7
	str	__ip, [__v2, #84]
	blt	|L..273|
|L..271|
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..301|
	ALIGN
|L..300|
	DCD	|bitindex|
	DCD	|wordpointer|
	DCD	|__stderr|
	DCD	|LC..0|
	DCD	|gainpow2|+2048
	DCD	|LC..1|
	DCD	|bandInfo|
|slen.17|
	KEEP |slen.17|
	DCB	0
	DCB	0
	DCB	0
	DCB	0
	DCB	3
	DCB	1
	DCB	1
	DCB	1
	DCB	2
	DCB	2
	DCB	2
	DCB	3
	DCB	3
	DCB	3
	DCB	4
	DCB	4
	DCB	0
	DCB	1
	DCB	2
	DCB	3
	DCB	0
	DCB	1
	DCB	2
	DCB	3
	DCB	1
	DCB	2
	DCB	3
	DCB	1
	DCB	2
	DCB	3
	DCB	2
	DCB	3
	ALIGN
|III_get_scale_factors_1|
	KEEP |III_get_scale_factors_1|
	; args = 0, pretend = 0, frame = 8, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	bllt	|__rt_stkovf_split_small|
	sub	__sp, __sp, #8
	ldr	__ip, |L..361|
	ldr	__a4, [__a2, #16]
	mov	__v2, __a1
	ldr	__a3, [__a2, #12]
	cmp	__a4, #2
	ldrb	__v3, [__ip, __a3]	; zero_extendqisi2
	add	__ip, __ip, #16
	ldrb	__v5, [__ip, __a3]	; zero_extendqisi2
	bne	|L..303|
	mov	__v1, #18
	add	__ip, __v3, __v5
	add	__ip, __ip, __ip, asl #3
	ldr	__a3, [__a2, #20]
	mov	__v4, __ip, asl #1
	cmp	__a3, #0
	beq	|L..304|
	sub	__v1, __v1, #10
	rsb	__v4, __v3, __v4
|L..308|
	mov	__a1, __v3
	bl	|getbits_fast|
	subs	__v1, __v1, #1
	str	__a1, [__v2], #4
	bne	|L..308|
	mov	__v1, #9
|L..304|
	cmp	__v1, #0
	beq	|L..311|
|L..313|
	mov	__a1, __v3
	bl	|getbits_fast|
	subs	__v1, __v1, #1
	str	__a1, [__v2], #4
	bne	|L..313|
|L..311|
	mov	__v1, #18
|L..318|
	mov	__a1, __v5
	bl	|getbits_fast|
	subs	__v1, __v1, #1
	str	__a1, [__v2], #4
	bne	|L..318|
	str	__v1, [__v2], #4
	str	__v1, [__v2], #4
	str	__v1, [__v2, #0]
	b	|L..320|
|L..303|
	ldr	__a2, [__a2, #0]
	cmp	__a2, #0
	bge	|L..321|
	mov	__v1, #11
	add	__v4, __v3, __v5
|L..325|
	mov	__a1, __v3
	bl	|getbits_fast|
	subs	__v1, __v1, #1
	str	__a1, [__v2], #4
	bne	|L..325|
	mov	__v1, #10
|L..330|
	mov	__a1, __v5
	bl	|getbits_fast|
	subs	__v1, __v1, #1
	str	__a1, [__v2], #4
	bne	|L..330|
	add	__ip, __v4, __v4, asl #2
	add	__v4, __v3, __ip, asl #1
	b	|L..332|
|L..321|
	mov	__v4, #0
	tst	__a2, #8
	bne	|L..333|
	mov	__v1, #6
	mov	__v4, __v3, asl #1
	and	__v6, __a2, #4
	and	__ip, __a2, #2
	str	__ip, [__sp, #4]
	and	__a2, __a2, #1
	str	__a2, [__sp, #0]
|L..337|
	mov	__a1, __v3
	bl	|getbits_fast|
	subs	__v1, __v1, #1
	str	__a1, [__v2], #4
	bne	|L..337|
	add	__ip, __v4, __v3
	mov	__v4, __ip, asl #1
	b	|L..339|
|L..333|
	add	__v2, __v2, #24
	and	__v6, __a2, #4
	and	__ip, __a2, #2
	str	__ip, [__sp, #4]
	and	__a2, __a2, #1
	str	__a2, [__sp, #0]
|L..339|
	cmp	__v6, #0
	bne	|L..340|
	mov	__v1, #5
	mov	__v6, __v3, asl #2
|L..344|
	mov	__a1, __v3
	bl	|getbits_fast|
	subs	__v1, __v1, #1
	str	__a1, [__v2], #4
	bne	|L..344|
	add	__ip, __v6, __v3
	add	__v4, __v4, __ip
	b	|L..346|
|L..340|
	add	__v2, __v2, #20
|L..346|
	ldr	__ip, [__sp, #4]
	cmp	__ip, #0
	bne	|L..347|
	mov	__v1, #5
	mov	__v3, __v5, asl #2
|L..351|
	mov	__a1, __v5
	bl	|getbits_fast|
	subs	__v1, __v1, #1
	str	__a1, [__v2], #4
	bne	|L..351|
	add	__ip, __v3, __v5
	add	__v4, __v4, __ip
	b	|L..353|
|L..347|
	add	__v2, __v2, #20
|L..353|
	ldr	__ip, [__sp, #0]
	cmp	__ip, #0
	bne	|L..354|
	mov	__v1, #5
	mov	__v3, __v5, asl #2
|L..358|
	mov	__a1, __v5
	bl	|getbits_fast|
	subs	__v1, __v1, #1
	str	__a1, [__v2], #4
	bne	|L..358|
	add	__ip, __v3, __v5
	add	__v4, __v4, __ip
	b	|L..332|
|L..354|
	add	__v2, __v2, #20
|L..332|
	mov	__ip, #0
	str	__ip, [__v2, #0]
|L..320|
	mov	__a1, __v4
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..362|
	ALIGN
|L..361|
	DCD	|slen.17|
|stab.21|
	KEEP |stab.21|
	DCB	6
	DCB	5
	DCB	5
	DCB	5
	DCB	6
	DCB	5
	DCB	7
	DCB	3
	DCB	11
	DCB	10
	DCB	0
	DCB	0
	DCB	7
	DCB	7
	DCB	7
	DCB	0
	DCB	6
	DCB	6
	DCB	6
	DCB	3
	DCB	8
	DCB	8
	DCB	5
	DCB	0
	DCB	9
	DCB	9
	DCB	9
	DCB	9
	DCB	9
	DCB	9
	DCB	12
	DCB	6
	DCB	18
	DCB	18
	DCB	0
	DCB	0
	DCB	12
	DCB	12
	DCB	12
	DCB	0
	DCB	12
	DCB	9
	DCB	9
	DCB	6
	DCB	15
	DCB	12
	DCB	9
	DCB	0
	DCB	6
	DCB	9
	DCB	9
	DCB	9
	DCB	6
	DCB	9
	DCB	12
	DCB	6
	DCB	15
	DCB	18
	DCB	0
	DCB	0
	DCB	6
	DCB	15
	DCB	12
	DCB	0
	DCB	6
	DCB	12
	DCB	9
	DCB	6
	DCB	6
	DCB	18
	DCB	9
	DCB	0
	ALIGN
|III_get_scale_factors_2|
	KEEP |III_get_scale_factors_2|
	; args = 0, pretend = 0, frame = 12, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	bllt	|__rt_stkovf_split_small|
	sub	__sp, __sp, #12
	mov	__a4, #0
	str	__a1, [__sp, #0]
	cmp	__a3, __a4
	str	__a4, [__sp, #4]
	beq	|L..364|
	ldr	__ip, [__a2, #12]
	ldr	__a3, |L..391|
	mov	__ip, __ip, lsr #1
	b	|L..390|
|L..364|
	ldr	__a3, |L..391|+4
	ldr	__ip, [__a2, #12]
|L..390|
	ldr	__v5, [__a3, __ip, asl #2]
	mov	__a3, #0
	mov	__ip, __v5, lsr #15
	ldr	__a4, [__a2, #16]
	and	__ip, __ip, #1
	str	__ip, [__a2, #76]
	cmp	__a4, #2
	bne	|L..366|
	ldr	__ip, [__a2, #20]
	cmp	__ip, __a3
	movne	__a3, __a4
	moveq	__a3, #1
|L..366|
	mov	__v3, #0
	mov	__ip, __a3, asl #1
	str	__ip, [__sp, #8]
	add	__ip, __ip, __a3
	mov	__a3, __v5, lsr #10
	ldr	__a4, |L..391|+8
	and	__a3, __a3, #28
	add	__a3, __a3, __a4
	add	__v4, __a3, __ip, asl #3
|L..371|
	and	__v2, __v5, #7
	mov	__v5, __v5, lsr #3
	cmp	__v2, #0
	beq	|L..372|
	mov	__v1, #0
	ldrb	__ip, [__v4, __v3]	; zero_extendqisi2
	add	__v6, __v3, #1
	cmp	__v1, __ip
	bge	|L..374|
|L..376|
	mov	__a1, __v2
	bl	|getbits_fast|
	ldrb	__ip, [__v4, __v3]	; zero_extendqisi2
	ldr	__a3, [__sp, #0]
	add	__v1, __v1, #1
	str	__a1, [__a3], #4
	cmp	__v1, __ip
	str	__a3, [__sp, #0]
	blt	|L..376|
|L..374|
	ldrb	__ip, [__v4, __v3]	; zero_extendqisi2
	ldr	__a4, [__sp, #4]
	mla	__a4, __v2, __ip, __a4
	str	__a4, [__sp, #4]
	b	|L..370|
|L..372|
	mov	__v1, __v2
	ldrb	__ip, [__v4, __v3]	; zero_extendqisi2
	add	__v6, __v3, #1
	cmp	__v1, __ip
	bge	|L..370|
	mov	__a3, __v1
|L..382|
	ldr	__a4, [__sp, #0]
	add	__v1, __v1, #1
	str	__a3, [__a4], #4
	cmp	__v1, __ip
	str	__a4, [__sp, #0]
	blt	|L..382|
|L..370|
	mov	__v3, __v6
	cmp	__v3, #3
	ble	|L..371|
	ldr	__ip, [__sp, #8]
	mov	__v3, #0
	add	__a3, __ip, #1
	cmp	__v3, __a3
	bge	|L..386|
	mov	__ip, __v3
|L..388|
	ldr	__a4, [__sp, #0]
	add	__v3, __v3, #1
	str	__ip, [__a4], #4
	cmp	__v3, __a3
	str	__a4, [__sp, #0]
	blt	|L..388|
|L..386|
	ldr	__a1, [__sp, #4]
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..392|
	ALIGN
|L..391|
	DCD	|i_slen2|
	DCD	|n_slen2|
	DCD	|stab.21|
	ALIGN
|pretab1|
	KEEP |pretab1|
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	1
	DCD	1
	DCD	1
	DCD	1
	DCD	2
	DCD	2
	DCD	3
	DCD	3
	DCD	3
	DCD	2
	DCD	0
	ALIGN
|pretab2|
	KEEP |pretab2|
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	ALIGN
|LC..2|
	DCB &6d, &70, &67, &31
	DCB &32, &33, &3a, &20
	DCB &43, &61, &6e, &27
	DCB &74, &20, &72, &65
	DCB &77, &69, &6e, &64
	DCB &20, &73, &74, &72
	DCB &65, &61, &6d, &20
	DCB &62, &79, &20, &25
	DCB &64, &20, &62, &69
	DCB &74, &73, &21, &0a
	DCB &00
	ALIGN
|III_dequantize_sample|
	KEEP |III_dequantize_sample|
	; args = 4, pretend = 0, frame = 144, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	bllt	|__rt_stkovf_split_small|
	sub	__sp, __sp, #144
	str	__a2, [__sp, #32]
	str	__a1, [__sp, #28]
	str	__a3, [__sp, #36]
	ldr	__ip, [__fp, #4]
	ldr	__a3, [__a3, #4]
	mov	__v4, __a1
	ldr	__a1, [__sp, #36]
	mov	__lr, #288
	ldr	__a2, [__a1, #80]
	cmp	__lr, #0
	str	__a4, [__sp, #40]
	rsb	__v3, __ip, __a3
	ldr	__a1, |L..577|
	add	__a2, __a2, #1
	str	__a2, [__sp, #44]
	ble	|L..395|
	adr	__a3, |L..577|+4
	ldmia	__a3, {__a3-__a4}
|L..397|
	stmia	__v4!, {__a3-__a4}
	sub	__lr, __lr, #1
	cmp	__lr, #0
	stmia	__v4!, {__a3-__a4}
	bgt	|L..397|
|L..395|
	ldr	__a3, [__sp, #36]
	ldr	__v4, [__sp, #28]
	ldr	__a2, [__a3, #8]
	ldr	__a3, [__a3, #68]
	rsb	__ip, __a2, #288
	mov	__ip, __ip, asr #1
	str	__ip, [__sp, #48]
	ldr	__ip, [__sp, #36]
	cmp	__a2, __a3
	ldr	__a4, [__ip, #72]
	bgt	|L..399|
	str	__a2, [__sp, #0]
	mov	__ip, #0
	str	__ip, [__sp, #4]
	str	__ip, [__sp, #8]
	b	|L..400|
|L..399|
	cmp	__a2, __a4
	str	__a3, [__sp, #0]
	bgt	|L..401|
	rsb	__ip, __a3, __a2
	str	__ip, [__sp, #4]
	mov	__a3, #0
	b	|L..564|
|L..401|
	rsb	__ip, __a3, __a4
	str	__ip, [__sp, #4]
	rsb	__a3, __a4, __a2
|L..564|
	str	__a3, [__sp, #8]
|L..400|
	ldr	__lr, [__sp, #36]
	ldr	__a3, [__lr, #16]
	cmp	__a3, #2
	bne	|L..403|
	mov	__a2, #0
	str	__a2, [__sp, #56]
	str	__a2, [__sp, #60]
	adr	__v5, |L..577|+4
	ldmia	__v5, {__v5-__v6}
	ldr	__ip, [__lr, #20]
	str	__a2, [__sp, #64]
	cmp	__ip, __a2
	beq	|L..404|
	str	__a3, [__sp, #20]
	str	__a3, [__sp, #16]
	str	__a3, [__sp, #12]
	ldr	__a3, [__sp, #40]
	mvn	__ip, #0
	str	__ip, [__sp, #24]
	mov	__a4, __a3, asl #1
	add	__ip, __a4, __a3
	mov	__ip, __ip, asl #2
	ldr	__a1, [__a1, __ip]
	ldr	__a3, |L..577|+12
	str	__a4, [__sp, #120]
	str	__a1, [__sp, #68]
	ldr	__a3, [__a3, __ip]
	str	__a3, [__sp, #52]
	b	|L..405|
|L..404|
	mvn	__ip, #0
	str	__ip, [__sp, #24]
	str	__ip, [__sp, #20]
	str	__ip, [__sp, #16]
	str	__ip, [__sp, #12]
	ldr	__a4, [__sp, #40]
	add	__ip, __a1, #4
	mov	__a2, __a4, asl #1
	add	__a3, __a2, __a4
	mov	__a3, __a3, asl #2
	ldr	__ip, [__ip, __a3]
	ldr	__a4, |L..577|+16
	str	__a2, [__sp, #120]
	str	__ip, [__sp, #68]
	ldr	__a4, [__a4, __a3]
	str	__a4, [__sp, #52]
|L..405|
	mov	__ip, #0
	ldr	__lr, [__sp, #36]
	mov	__v2, __ip
	str	__ip, [__sp, #72]
	add	__lr, __lr, #24
	str	__lr, [__sp, #124]
|L..409|
	mov	__ip, __v2, asl #2
	ldr	__a2, [__sp, __ip]
	ldr	__a1, [__sp, #124]
	ldr	__a4, |L..577|+20
	add	__v2, __v2, #1
	ldr	__a3, [__a1, __ip]
	cmp	__a2, #0
	str	__v2, [__sp, #128]
	add	__a3, __a4, __a3, asl #3
	str	__a3, [__sp, #76]
	beq	|L..408|
|L..413|
	ldr	__ip, [__sp, #72]
	cmp	__ip, #0
	bne	|L..414|
	ldr	__lr, [__sp, #68]
	ldr	__a4, [__sp, #28]
	ldr	__a1, [__lr], #4
	str	__a1, [__sp, #72]
	ldr	__ip, [__lr], #4
	ldr	__a3, [__lr], #4
	str	__a3, [__sp, #60]
	add	__v4, __a4, __ip, asl #3
	ldr	__ip, [__lr], #4
	str	__ip, [__sp, #64]
	cmp	__a3, #3
	str	__lr, [__sp, #68]
	bne	|L..415|
	ldr	__lr, [__sp, #32]
	ldr	__a4, [__sp, #36]
	ldr	__a3, [__lr], #4
	mov	__a1, #1
	str	__a1, [__sp, #56]
	str	__lr, [__sp, #32]
	ldr	__lr, [__sp, #44]
	ldr	__ip, [__a4, #100]
	mov	__a3, __a3, asl __lr
	add	__ip, __ip, __a3, asl #3
	ldmia	__ip, {__v5-__v6}
	b	|L..414|
|L..415|
	mov	__a1, #3
	str	__a1, [__sp, #56]
	ldr	__a3, [__sp, #32]
	ldr	__a4, [__sp, #36]
	ldr	__lr, [__sp, #60]
	ldr	__a1, [__sp, #44]
	ldr	__ip, [__a3], #4
	str	__a3, [__sp, #32]
	add	__a3, __a4, #88
	ldr	__a4, [__a3, __lr, asl #2]
	mov	__ip, __ip, asl __a1
	add	__a4, __a4, __ip, asl #3
	ldmia	__a4, {__v5-__v6}
|L..414|
	ldr	__a3, [__sp, #76]
	ldr	__a4, [__sp, #56]
	ldr	__a1, [__a3, #4]
	ldr	__ip, [__a1], #2	; movhi
	mov	__a4, __a4, asl #3
	str	__a4, [__sp, #136]
	mov	__ip, __ip, asl #16
	movs	__v2, __ip, asr #16
	ldr	__ip, [__sp, #72]
	sub	__a2, __a2, #1
	str	__a2, [__sp, #140]
	sub	__ip, __ip, #1
	str	__ip, [__sp, #132]
	bpl	|L..418|
	ldr	__v1, |L..577|+24
	ldr	__lr, |L..577|+28
|L..419|
	ldr	__a2, [__lr, #0]
	ldr	__ip, [__v1, #0]
	add	__a3, __a2, #1
	ldrb	__a4, [__ip, #0]	; zero_extendqisi2
	add	__ip, __ip, __a3, asr #3
	str	__ip, [__v1, #0]
	and	__a3, __a3, #7
	str	__a3, [__lr, #0]
	mov	__a4, __a4, asl __a2
	tst	__a4, #128
	subne	__a1, __a1, __v2, asl #1
|L..420|
	ldr	__ip, [__a1], #2	; movhi
	sub	__v3, __v3, #1
	mov	__ip, __ip, asl #16
	movs	__v2, __ip, asr #16
	bmi	|L..419|
|L..418|
	mov	__v1, __v2, asr #4
	and	__v2, __v2, #15
	cmp	__v1, #15
	bne	|L..423|
	ldr	__a1, [__sp, #64]
	ldr	__lr, [__sp, #60]
	add	__ip, __sp, #12
	str	__a1, [__ip, __lr, asl #2]
	ldr	__a2, [__sp, #76]
	ldr	__a1, [__a2, #0]
	sub	__ip, __v3, #1
	rsb	__v3, __a1, __ip
	bl	|getbits|
	ldr	__a3, |L..577|+28
	ldr	__a4, |L..577|+24
	ldr	__lr, |L..577|+24
	add	__v1, __a1, __v1
	ldr	__a1, |L..577|+28
	ldr	__a2, [__a3, #0]
	ldr	__ip, [__a4, #0]
	add	__a3, __a2, #1
	ldrb	__a4, [__ip, #0]	; zero_extendqisi2
	add	__ip, __ip, __a3, asr #3
	str	__ip, [__lr, #0]
	and	__a3, __a3, #7
	str	__a3, [__a1, #0]
	mov	__a4, __a4, asl __a2
	tst	__a4, #128
	beq	|L..424|
	ldr	__a2, |L..577|+32
	add	__ip, __a2, __v1, asl #3
	ldmia	__ip, {__a1-__a2}
	bl	|__negdf2|
	b	|L..565|
|L..424|
	ldr	__a3, |L..577|+32
	add	__ip, __a3, __v1, asl #3
	ldmia	__ip, {__a1-__a2}
|L..565|
	mov	__a4, __v6
	mov	__a3, __v5
	bl	|__muldf3|
	stmia	__v4, {__a1-__a2}
	b	|L..427|
|L..423|
	cmp	__v1, #0
	beq	|L..428|
	ldr	__lr, [__sp, #64]
	ldr	__a4, [__sp, #60]
	ldr	__a1, |L..577|+28
	ldr	__a3, |L..577|+24
	add	__ip, __sp, #12
	str	__lr, [__ip, __a4, asl #2]
	ldr	__ip, [__a3, #0]
	ldr	__lr, |L..577|+24
	ldr	__a2, [__a1, #0]
	ldrb	__a4, [__ip, #0]	; zero_extendqisi2
	add	__a3, __a2, #1
	add	__ip, __ip, __a3, asr #3
	and	__a3, __a3, #7
	mov	__a4, __a4, asl __a2
	str	__ip, [__lr, #0]
	tst	__a4, #128
	str	__a3, [__a1, #0]
	beq	|L..429|
	ldr	__a1, |L..577|+32
	add	__ip, __a1, __v1, asl #3
	ldmia	__ip, {__a1-__a2}
	bl	|__negdf2|
	b	|L..566|
|L..578|
	ALIGN
|L..577|
	DCD	|map|
	DCD &0, &0	; double 0.00000000000000000000e0
	DCD	|mapend|
	DCD	|mapend|+4
	DCD	|ht|
	DCD	|wordpointer|
	DCD	|bitindex|
	DCD	|ispow|
|L..429|
	ldr	__a2, |L..579|
	add	__ip, __a2, __v1, asl #3
	ldmia	__ip, {__a1-__a2}
|L..566|
	mov	__a4, __v6
	mov	__a3, __v5
	bl	|__muldf3|
	stmia	__v4, {__a1-__a2}
	sub	__v3, __v3, #1
	b	|L..427|
|L..428|
	adr	__a3, |L..579|+4
	ldmia	__a3, {__a3-__a4}
	stmia	__v4, {__a3-__a4}
|L..427|
	ldr	__a4, [__sp, #136]
	cmp	__v2, #15
	add	__v4, __v4, __a4
	bne	|L..433|
	ldr	__a1, [__sp, #64]
	ldr	__lr, [__sp, #60]
	add	__ip, __sp, #12
	str	__a1, [__ip, __lr, asl #2]
	ldr	__a2, [__sp, #76]
	ldr	__a1, [__a2, #0]
	sub	__ip, __v3, #1
	rsb	__v3, __a1, __ip
	bl	|getbits|
	ldr	__a3, |L..579|+12
	ldr	__a4, |L..579|+16
	ldr	__lr, |L..579|+16
	add	__v2, __a1, __v2
	ldr	__a1, |L..579|+12
	ldr	__a2, [__a3, #0]
	ldr	__ip, [__a4, #0]
	add	__a3, __a2, #1
	ldrb	__a4, [__ip, #0]	; zero_extendqisi2
	add	__ip, __ip, __a3, asr #3
	str	__ip, [__lr, #0]
	and	__a3, __a3, #7
	str	__a3, [__a1, #0]
	mov	__a4, __a4, asl __a2
	tst	__a4, #128
	beq	|L..434|
	ldr	__a2, |L..579|
	add	__ip, __a2, __v2, asl #3
	ldmia	__ip, {__a1-__a2}
	bl	|__negdf2|
	b	|L..567|
|L..434|
	ldr	__a3, |L..579|
	add	__ip, __a3, __v2, asl #3
	ldmia	__ip, {__a1-__a2}
|L..567|
	mov	__a4, __v6
	mov	__a3, __v5
	bl	|__muldf3|
	stmia	__v4, {__a1-__a2}
	b	|L..437|
|L..433|
	cmp	__v2, #0
	beq	|L..438|
	ldr	__lr, [__sp, #64]
	ldr	__a4, [__sp, #60]
	ldr	__a1, |L..579|+12
	ldr	__a3, |L..579|+16
	add	__ip, __sp, #12
	str	__lr, [__ip, __a4, asl #2]
	ldr	__ip, [__a3, #0]
	ldr	__lr, |L..579|+16
	ldr	__a2, [__a1, #0]
	ldrb	__a4, [__ip, #0]	; zero_extendqisi2
	add	__a3, __a2, #1
	add	__ip, __ip, __a3, asr #3
	and	__a3, __a3, #7
	mov	__a4, __a4, asl __a2
	str	__ip, [__lr, #0]
	tst	__a4, #128
	str	__a3, [__a1, #0]
	beq	|L..439|
	ldr	__a1, |L..579|
	add	__ip, __a1, __v2, asl #3
	ldmia	__ip, {__a1-__a2}
	bl	|__negdf2|
	b	|L..568|
|L..439|
	ldr	__a2, |L..579|
	add	__ip, __a2, __v2, asl #3
	ldmia	__ip, {__a1-__a2}
|L..568|
	mov	__a4, __v6
	mov	__a3, __v5
	bl	|__muldf3|
	stmia	__v4, {__a1-__a2}
	sub	__v3, __v3, #1
	b	|L..437|
|L..438|
	adr	__a3, |L..579|+4
	ldmia	__a3, {__a3-__a4}
	stmia	__v4, {__a3-__a4}
|L..437|
	ldr	__a4, [__sp, #136]
	ldr	__ip, [__sp, #132]
	ldr	__a2, [__sp, #140]
	add	__v4, __v4, __a4
	cmp	__a2, #0
	str	__ip, [__sp, #72]
	bne	|L..413|
|L..408|
	ldr	__v2, [__sp, #128]
	cmp	__v2, #1
	ble	|L..409|
	ldr	__lr, [__sp, #48]
	cmp	__lr, #0
	cmpne	__v3, #0
	ble	|L..559|
|L..448|
	ldr	__a1, [__sp, #36]
	ldr	__a3, |L..579|+20
	ldr	__ip, [__a1, #84]
	ldr	__a2, [__sp, #48]
	add	__a3, __a3, __ip, asl #3
	ldr	__a1, [__a3, #4]
	ldr	__ip, [__a1], #2	; movhi
	sub	__a2, __a2, #1
	str	__a2, [__sp, #116]
	b	|L..569|
|L..562|
	add	__v3, __v3, #1
	b	|L..447|
|L..452|
	ldr	__a3, |L..579|+16
	ldr	__a2, |L..579|+12
	ldr	__a4, [__a3, #0]
	ldr	__ip, [__a2, #0]
	ldrb	__a3, [__a4, #0]	; zero_extendqisi2
	ldr	__lr, |L..579|+16
	mov	__a3, __a3, asl __ip
	tst	__a3, #128
	add	__ip, __ip, #1
	add	__a4, __a4, __ip, asr #3
	str	__a4, [__lr, #0]
	and	__ip, __ip, #7
	str	__ip, [__a2, #0]
	subne	__a1, __a1, __v1, asl #1
|L..449|
	ldr	__ip, [__a1], #2	; movhi
|L..569|
	mov	__ip, __ip, asl #16
	movs	__v1, __ip, asr #16
	bpl	|L..450|
	subs	__v3, __v3, #1
	bpl	|L..452|
	add	__v3, __v3, #1
	mov	__v1, #0
|L..450|
	mov	__v2, #0
|L..459|
	tst	__v2, #1
	bne	|L..460|
	ldr	__a1, [__sp, #72]
	cmp	__a1, #0
	bne	|L..461|
	ldr	__a2, [__sp, #68]
	ldr	__lr, [__sp, #28]
	ldr	__a3, [__a2], #4
	str	__a3, [__sp, #72]
	ldr	__ip, [__a2], #4
	ldr	__a4, [__a2], #4
	str	__a4, [__sp, #60]
	ldr	__a1, [__a2], #4
	add	__v4, __lr, __ip, asl #3
	str	__a1, [__sp, #64]
	cmp	__a4, #3
	str	__a2, [__sp, #68]
	bne	|L..462|
	ldr	__a2, [__sp, #32]
	ldr	__lr, [__sp, #36]
	ldr	__a1, [__sp, #44]
	ldr	__a3, [__a2], #4
	mov	__a4, #1
	str	__a4, [__sp, #56]
	str	__a2, [__sp, #32]
	ldr	__ip, [__lr, #100]
	mov	__a3, __a3, asl __a1
	add	__ip, __ip, __a3, asl #3
	ldmia	__ip, {__v5-__v6}
	b	|L..461|
|L..462|
	mov	__a2, #3
	str	__a2, [__sp, #56]
	ldr	__a3, [__sp, #32]
	ldr	__a4, [__sp, #36]
	ldr	__lr, [__sp, #60]
	ldr	__a1, [__sp, #44]
	ldr	__ip, [__a3], #4
	str	__a3, [__sp, #32]
	add	__a3, __a4, #88
	ldr	__a4, [__a3, __lr, asl #2]
	mov	__ip, __ip, asl __a1
	add	__a4, __a4, __ip, asl #3
	ldmia	__a4, {__v5-__v6}
|L..461|
	ldr	__a2, [__sp, #72]
	sub	__a2, __a2, #1
	str	__a2, [__sp, #72]
|L..460|
	mov	__ip, #8
	ands	__ip, __v1, __ip, asr __v2
	beq	|L..464|
	ldr	__a4, [__sp, #64]
	subs	__v3, __v3, #1
	ldr	__a3, [__sp, #60]
	add	__ip, __sp, #12
	str	__a4, [__ip, __a3, asl #2]
	bmi	|L..562|
	ldr	__ip, |L..579|+12
	ldr	__lr, |L..579|+16
	ldr	__a1, |L..579|+12
	ldr	__a2, [__ip, #0]
	ldr	__ip, [__lr, #0]
	add	__a3, __a2, #1
	ldrb	__a4, [__ip, #0]	; zero_extendqisi2
	add	__ip, __ip, __a3, asr #3
	str	__ip, [__lr, #0]
	and	__a3, __a3, #7
	str	__a3, [__a1, #0]
	mov	__a4, __a4, asl __a2
	tst	__a4, #128
	beq	|L..466|
	mov	__a2, __v6
	mov	__a1, __v5
	bl	|__negdf2|
	stmia	__v4, {__a1-__a2}
	b	|L..469|
|L..466|
	stmia	__v4, {__v5-__v6}
	b	|L..469|
|L..580|
	ALIGN
|L..579|
	DCD	|ispow|
	DCD &0, &0	; double 0.00000000000000000000e0
	DCD	|bitindex|
	DCD	|wordpointer|
	DCD	|htc|
|L..464|
	adr	__a2, |L..581|
	ldmia	__a2, {__a2-__a3}
	stmia	__v4, {__a2-__a3}
|L..469|
	add	__v2, __v2, #1
	ldr	__a3, [__sp, #56]
	cmp	__v2, #3
	add	__v4, __v4, __a3, asl #3
	ble	|L..459|
|L..447|
	ldr	__a4, [__sp, #116]
	str	__a4, [__sp, #48]
	cmp	__a4, #0
	cmpne	__v3, #0
	bgt	|L..448|
|L..559|
	ldr	__ip, [__sp, #68]
	ldr	__lr, [__sp, #52]
	cmp	__ip, __lr
	bcs	|L..560|
	adr	__a4, |L..581|
	ldmia	__a4, {__a4-__v1}
|L..474|
	ldr	__a1, [__sp, #72]
	cmp	__a1, #0
	bne	|L..475|
	ldr	__a2, [__sp, #68]
	ldr	__lr, [__sp, #28]
	ldr	__a3, [__a2], #4
	str	__a3, [__sp, #72]
	ldr	__a3, [__a2], #4
	ldr	__ip, [__a2], #4
	add	__v4, __lr, __a3, asl #3
	cmp	__ip, #3
	movne	__ip, #3
	moveq	__ip, #1
	str	__ip, [__sp, #56]
	add	__a2, __a2, #4
	str	__a2, [__sp, #68]
|L..475|
	ldr	__a1, [__sp, #72]
	sub	__a1, __a1, #1
	str	__a1, [__sp, #72]
	stmia	__v4, {__a4-__v1}
	ldr	__a2, [__sp, #56]
	mov	__ip, __a2, asl #3
	add	__v4, __v4, __ip
	stmia	__v4, {__a4-__v1}
	ldr	__a3, [__sp, #68]
	add	__v4, __v4, __ip
	ldr	__ip, [__sp, #52]
	cmp	__a3, __ip
	bcc	|L..474|
|L..560|
	ldr	__a2, [__sp, #12]
	ldr	__a3, [__sp, #16]
	ldr	__lr, [__sp, #36]
	add	__ip, __a2, #1
	str	__ip, [__lr, #48]
	cmp	__a3, __a2
	movge	__a2, __a3
	ldr	__a4, [__sp, #20]
	add	__a3, __a3, #1
	str	__a3, [__lr, #52]
	ldr	__a3, [__sp, #24]
	cmp	__a4, __a2
	movge	__ip, __a4
	movlt	__ip, __a2
	adds	__a2, __ip, #1
	add	__a4, __a4, #1
	str	__a4, [__lr, #56]
	add	__a1, __a3, #1
	str	__a1, [__lr, #60]
	beq	|L..479|
	ldr	__a1, [__sp, #40]
	ldr	__a3, |L..581|+8
	rsb	__ip, __a1, __a1, asl #3
	mov	__ip, __ip, asl #3
	add	__ip, __ip, __a2, asl #2
	b	|L..570|
|L..479|
	ldr	__a2, [__sp, #120]
	ldr	__a3, [__sp, #40]
	add	__ip, __a2, __a3
	rsb	__ip, __a3, __ip, asl #3
	mov	__ip, __ip, asl #2
	ldr	__a3, |L..581|+12
	add	__ip, __ip, __a1, asl #2
|L..570|
	ldr	__a2, [__a3, __ip]
	ldr	__a4, [__sp, #36]
	str	__a2, [__a4, #64]
	b	|L..576|
|L..403|
	mvn	__ip, #0
	str	__ip, [__sp, #84]
	mov	__lr, #0
	str	__lr, [__sp, #88]
	ldr	__a2, |L..581|+16
	ldr	__a3, [__sp, #40]
	add	__ip, __a1, #8
	adr	__v5, |L..581|
	ldmia	__v5, {__v5-__v6}
	mov	__a4, __a3, asl #1
	add	__a3, __a4, __a3
	ldr	__a3, [__ip, __a3, asl #2]
	str	__lr, [__sp, #96]
	ldr	__ip, [__sp, #36]
	mov	__v1, __lr
	ldr	__lr, [__sp, #36]
	str	__a3, [__sp, #92]
	ldr	__a3, [__ip, #76]
	str	__a4, [__sp, #120]
	ldr	__ip, |L..581|+20
	add	__lr, __lr, #24
	str	__lr, [__sp, #124]
	cmp	__a3, #0
	movne	__a2, __ip
	str	__a2, [__sp, #80]
|L..487|
	mov	__ip, __v1, asl #2
	ldr	__a2, [__sp, __ip]
	ldr	__a1, [__sp, #124]
	ldr	__a4, |L..581|+24
	add	__v1, __v1, #1
	ldr	__a3, [__a1, __ip]
	cmp	__a2, #0
	str	__v1, [__sp, #104]
	add	__a3, __a4, __a3, asl #3
	str	__a3, [__sp, #100]
	beq	|L..486|
|L..491|
	ldr	__ip, [__sp, #96]
	cmp	__ip, #0
	bne	|L..492|
	ldr	__lr, [__sp, #32]
	ldr	__a1, [__sp, #80]
	ldr	__a3, [__sp, #92]
	ldr	__ip, [__lr], #4
	str	__lr, [__sp, #32]
	ldr	__a4, [__a1], #4
	str	__a1, [__sp, #80]
	ldr	__a1, [__sp, #36]
	add	__ip, __ip, __a4
	ldr	__a4, [__sp, #44]
	ldr	__lr, [__a3], #4
	str	__lr, [__sp, #96]
	str	__a3, [__sp, #92]
	ldr	__a3, [__a1, #100]
	mov	__ip, __ip, asl __a4
	add	__a3, __a3, __ip, asl #3
	ldr	__ip, [__sp, #92]
	ldmia	__a3, {__v5-__v6}
	ldr	__lr, [__ip], #4
	str	__lr, [__sp, #88]
	str	__ip, [__sp, #92]
|L..492|
	ldr	__a3, [__sp, #100]
	ldr	__a4, [__sp, #96]
	ldr	__a1, [__a3, #4]
	ldr	__ip, [__a1], #2	; movhi
	sub	__a2, __a2, #1
	str	__a2, [__sp, #112]
	sub	__a4, __a4, #1
	str	__a4, [__sp, #108]
	mov	__ip, __ip, asl #16
	movs	__v2, __ip, asr #16
	bpl	|L..494|
	ldr	__v1, |L..581|+28
	ldr	__lr, |L..581|+32
|L..495|
	ldr	__a2, [__lr, #0]
	ldr	__ip, [__v1, #0]
	add	__a3, __a2, #1
	ldrb	__a4, [__ip, #0]	; zero_extendqisi2
	add	__ip, __ip, __a3, asr #3
	str	__ip, [__v1, #0]
	and	__a3, __a3, #7
	str	__a3, [__lr, #0]
	mov	__a4, __a4, asl __a2
	tst	__a4, #128
	subne	__a1, __a1, __v2, asl #1
|L..496|
	ldr	__ip, [__a1], #2	; movhi
	sub	__v3, __v3, #1
	mov	__ip, __ip, asl #16
	movs	__v2, __ip, asr #16
	bmi	|L..495|
|L..494|
	mov	__v1, __v2, asr #4
	and	__v2, __v2, #15
	cmp	__v1, #15
	bne	|L..499|
	ldr	__ip, [__sp, #88]
	ldr	__lr, [__sp, #100]
	str	__ip, [__sp, #84]
	ldr	__a1, [__lr, #0]
	sub	__ip, __v3, #1
	rsb	__v3, __a1, __ip
	bl	|getbits|
	ldr	__a3, |L..581|+32
	ldr	__a4, |L..581|+28
	ldr	__lr, |L..581|+28
	add	__v1, __a1, __v1
	ldr	__a1, |L..581|+32
	ldr	__a2, [__a3, #0]
	ldr	__ip, [__a4, #0]
	add	__a3, __a2, #1
	ldrb	__a4, [__ip, #0]	; zero_extendqisi2
	add	__ip, __ip, __a3, asr #3
	str	__ip, [__lr, #0]
	and	__a3, __a3, #7
	str	__a3, [__a1, #0]
	mov	__a4, __a4, asl __a2
	tst	__a4, #128
	beq	|L..500|
	ldr	__a2, |L..581|+36
	add	__ip, __a2, __v1, asl #3
	ldmia	__ip, {__a1-__a2}
	bl	|__negdf2|
	mov	__a4, __v6
	mov	__a3, __v5
	bl	|__muldf3|
	b	|L..571|
|L..500|
	ldr	__a3, |L..581|+36
	add	__ip, __a3, __v1, asl #3
	ldmia	__ip, {__a1-__a2}
	mov	__a4, __v6
	mov	__a3, __v5
	bl	|__muldf3|
	b	|L..571|
|L..499|
	cmp	__v1, #0
	beq	|L..504|
	ldr	__a4, |L..581|+32
	ldr	__ip, [__sp, #88]
	ldr	__lr, |L..581|+28
	ldr	__a1, |L..581|+32
	ldr	__a2, [__a4, #0]
	str	__ip, [__sp, #84]
	ldr	__ip, [__lr, #0]
	add	__a3, __a2, #1
	ldrb	__a4, [__ip, #0]	; zero_extendqisi2
	add	__ip, __ip, __a3, asr #3
	str	__ip, [__lr, #0]
	and	__a3, __a3, #7
	str	__a3, [__a1, #0]
	mov	__a4, __a4, asl __a2
	tst	__a4, #128
	beq	|L..505|
	ldr	__a2, |L..581|+36
	add	__ip, __a2, __v1, asl #3
	ldmia	__ip, {__a1-__a2}
	bl	|__negdf2|
	b	|L..572|
|L..582|
	ALIGN
|L..581|
	DCD &0, &0	; double 0.00000000000000000000e0
	DCD	|shortLimit|
	DCD	|longLimit|
	DCD	|pretab2|
	DCD	|pretab1|
	DCD	|ht|
	DCD	|wordpointer|
	DCD	|bitindex|
	DCD	|ispow|
|L..505|
	ldr	__a3, |L..583|
	add	__ip, __a3, __v1, asl #3
	ldmia	__ip, {__a1-__a2}
|L..572|
	mov	__a4, __v6
	mov	__a3, __v5
	bl	|__muldf3|
	stmia	__v4!, {__a1-__a2}
	sub	__v3, __v3, #1
	b	|L..503|
|L..504|
	adr	__a1, |L..583|+4
	ldmia	__a1, {__a1-__a2}
|L..571|
	stmia	__v4!, {__a1-__a2}
|L..503|
	cmp	__v2, #15
	bne	|L..509|
	ldr	__a2, [__sp, #88]
	ldr	__a3, [__sp, #100]
	str	__a2, [__sp, #84]
	ldr	__a1, [__a3, #0]
	sub	__ip, __v3, #1
	rsb	__v3, __a1, __ip
	bl	|getbits|
	ldr	__a4, |L..583|+12
	ldr	__lr, |L..583|+16
	add	__v2, __a1, __v2
	ldr	__a1, |L..583|+12
	ldr	__a2, [__a4, #0]
	ldr	__ip, [__lr, #0]
	add	__a3, __a2, #1
	ldrb	__a4, [__ip, #0]	; zero_extendqisi2
	add	__ip, __ip, __a3, asr #3
	str	__ip, [__lr, #0]
	and	__a3, __a3, #7
	str	__a3, [__a1, #0]
	mov	__a4, __a4, asl __a2
	tst	__a4, #128
	beq	|L..510|
	ldr	__a2, |L..583|
	add	__ip, __a2, __v2, asl #3
	ldmia	__ip, {__a1-__a2}
	bl	|__negdf2|
	mov	__a4, __v6
	mov	__a3, __v5
	bl	|__muldf3|
	b	|L..573|
|L..510|
	ldr	__a3, |L..583|
	add	__ip, __a3, __v2, asl #3
	ldmia	__ip, {__a1-__a2}
	mov	__a4, __v6
	mov	__a3, __v5
	bl	|__muldf3|
	b	|L..573|
|L..509|
	cmp	__v2, #0
	beq	|L..514|
	ldr	__a4, |L..583|+12
	ldr	__ip, [__sp, #88]
	ldr	__lr, |L..583|+16
	ldr	__a1, |L..583|+12
	ldr	__a2, [__a4, #0]
	str	__ip, [__sp, #84]
	ldr	__ip, [__lr, #0]
	add	__a3, __a2, #1
	ldrb	__a4, [__ip, #0]	; zero_extendqisi2
	add	__ip, __ip, __a3, asr #3
	str	__ip, [__lr, #0]
	and	__a3, __a3, #7
	str	__a3, [__a1, #0]
	mov	__a4, __a4, asl __a2
	tst	__a4, #128
	beq	|L..515|
	ldr	__a2, |L..583|
	add	__ip, __a2, __v2, asl #3
	ldmia	__ip, {__a1-__a2}
	bl	|__negdf2|
	b	|L..574|
|L..515|
	ldr	__a3, |L..583|
	add	__ip, __a3, __v2, asl #3
	ldmia	__ip, {__a1-__a2}
|L..574|
	mov	__a4, __v6
	mov	__a3, __v5
	bl	|__muldf3|
	stmia	__v4!, {__a1-__a2}
	sub	__v3, __v3, #1
	b	|L..490|
|L..514|
	adr	__a1, |L..583|+4
	ldmia	__a1, {__a1-__a2}
|L..573|
	stmia	__v4!, {__a1-__a2}
|L..490|
	ldr	__a2, [__sp, #108]
	str	__a2, [__sp, #96]
	ldr	__a2, [__sp, #112]
	cmp	__a2, #0
	bne	|L..491|
|L..486|
	ldr	__v1, [__sp, #104]
	cmp	__v1, #2
	ble	|L..487|
	ldr	__a3, [__sp, #48]
	cmp	__a3, #0
	cmpne	__v3, #0
	ble	|L..561|
|L..524|
	ldr	__a4, [__sp, #36]
	ldr	__a3, |L..583|+20
	ldr	__ip, [__a4, #84]
	ldr	__lr, [__sp, #48]
	add	__a3, __a3, __ip, asl #3
	ldr	__a1, [__a3, #4]
	ldr	__ip, [__a1], #2	; movhi
	sub	__lr, __lr, #1
	str	__lr, [__sp, #116]
	b	|L..575|
|L..563|
	add	__v3, __v3, #1
	b	|L..523|
|L..528|
	ldr	__a3, |L..583|+12
	ldr	__a4, |L..583|+16
	ldr	__lr, |L..583|+16
	ldr	__a2, [__a3, #0]
	ldr	__ip, [__a4, #0]
	add	__a3, __a2, #1
	ldrb	__a4, [__ip, #0]	; zero_extendqisi2
	add	__ip, __ip, __a3, asr #3
	str	__ip, [__lr, #0]
	and	__a3, __a3, #7
	ldr	__ip, |L..583|+12
	mov	__a4, __a4, asl __a2
	tst	__a4, #128
	str	__a3, [__ip, #0]
	subne	__a1, __a1, __v2, asl #1
|L..525|
	ldr	__ip, [__a1], #2	; movhi
|L..575|
	mov	__ip, __ip, asl #16
	movs	__v2, __ip, asr #16
	bpl	|L..526|
	subs	__v3, __v3, #1
	bpl	|L..528|
	add	__v3, __v3, #1
	mov	__v2, #0
|L..526|
	mov	__v1, #0
|L..535|
	tst	__v1, #1
	bne	|L..536|
	ldr	__lr, [__sp, #96]
	cmp	__lr, #0
	bne	|L..537|
	ldr	__a1, [__sp, #92]
	ldr	__a3, [__sp, #32]
	ldr	__lr, [__sp, #80]
	ldr	__a2, [__a1], #4
	str	__a2, [__sp, #96]
	ldr	__ip, [__a3], #4
	str	__a3, [__sp, #32]
	ldr	__a4, [__lr], #4
	str	__lr, [__sp, #80]
	add	__ip, __ip, __a4
	ldr	__a4, [__sp, #36]
	ldr	__lr, [__sp, #44]
	ldr	__a2, [__a1], #4
	str	__a2, [__sp, #88]
	str	__a1, [__sp, #92]
	ldr	__a3, [__a4, #100]
	mov	__ip, __ip, asl __lr
	add	__a3, __a3, __ip, asl #3
	ldmia	__a3, {__v5-__v6}
|L..537|
	ldr	__a1, [__sp, #96]
	sub	__a1, __a1, #1
	str	__a1, [__sp, #96]
|L..536|
	mov	__ip, #8
	ands	__ip, __v2, __ip, asr __v1
	beq	|L..538|
	ldr	__a2, [__sp, #88]
	subs	__v3, __v3, #1
	str	__a2, [__sp, #84]
	bmi	|L..563|
	ldr	__a3, |L..583|+12
	ldr	__a4, |L..583|+16
	ldr	__lr, |L..583|+16
	ldr	__a1, |L..583|+12
	ldr	__a2, [__a3, #0]
	ldr	__ip, [__a4, #0]
	add	__a3, __a2, #1
	ldrb	__a4, [__ip, #0]	; zero_extendqisi2
	add	__ip, __ip, __a3, asr #3
	str	__ip, [__lr, #0]
	and	__a3, __a3, #7
	str	__a3, [__a1, #0]
	mov	__a4, __a4, asl __a2
	tst	__a4, #128
	beq	|L..540|
	mov	__a2, __v6
	mov	__a1, __v5
	bl	|__negdf2|
	stmia	__v4!, {__a1-__a2}
	b	|L..534|
|L..540|
	stmia	__v4!, {__v5-__v6}
	b	|L..534|
|L..538|
	adr	__a2, |L..583|+4
	ldmia	__a2, {__a2-__a3}
	stmia	__v4!, {__a2-__a3}
|L..534|
	add	__v1, __v1, #1
	cmp	__v1, #3
	ble	|L..535|
|L..523|
	ldr	__a3, [__sp, #116]
	str	__a3, [__sp, #48]
	cmp	__a3, #0
	cmpne	__v3, #0
	bgt	|L..524|
|L..561|
	ldr	__a4, [__sp, #28]
	sub	__ip, __v4, #4608
	rsb	__ip, __ip, __a4
	movs	__v1, __ip, asr #4
	ldr	__ip, [__sp, #84]
	add	__a2, __ip, #1
	beq	|L..547|
	adr	__a3, |L..583|+4
	ldmia	__a3, {__a3-__a4}
|L..549|
	stmia	__v4!, {__a3-__a4}
	subs	__v1, __v1, #1
	stmia	__v4!, {__a3-__a4}
	bne	|L..549|
|L..547|
	ldr	__lr, [__sp, #36]
	str	__a2, [__lr, #60]
	ldr	__a1, [__sp, #120]
	ldr	__a3, [__sp, #40]
	add	__ip, __a1, __a3
	rsb	__ip, __a3, __ip, asl #3
	mov	__ip, __ip, asl #2
	ldr	__a3, |L..583|+24
	add	__ip, __ip, __a2, asl #2
	ldr	__a4, [__a3, __ip]
	str	__a4, [__lr, #64]
	b	|L..576|
|L..584|
	ALIGN
|L..583|
	DCD	|ispow|
	DCD &0, &0	; double 0.00000000000000000000e0
	DCD	|bitindex|
	DCD	|wordpointer|
	DCD	|htc|
	DCD	|longLimit|
|L..553|
	mov	__a1, #16
	bl	|getbits|
	sub	__v3, __v3, #16
|L..576|
	cmp	__v3, #16
	bgt	|L..553|
	cmp	__v3, #0
	bgt	|L..555|
	bge	|L..556|
	ldr	__ip, |L..585|
	ldr	__a2, |L..585|+4
	ldr	__a1, [__ip, #0]
	rsb	__a3, __v3, #0
	bl	|fprintf|
	mov	__a1, #1
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..555|
	mov	__a1, __v3
	bl	|getbits|
|L..556|
	mov	__a1, #0
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..586|
	ALIGN
|L..585|
	DCD	|__stderr|
	DCD	|LC..2|
	ALIGN
|III_i_stereo|
	KEEP |III_i_stereo|
	; args = 8, pretend = 0, frame = 120, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	bllt	|__rt_stkovf_split_small|
	sub	__sp, __sp, #120
	ldr	__ip, [__fp, #8]
	stmia	__sp, {__a1, __a2, __a3}	; phole stm
	cmp	__ip, #0
	ldr	__ip, |L..652|
	add	__a4, __a4, __a4, asl #3
	ldr	__a3, [__fp, #4]
	add	__a4, __ip, __a4, asl #4
	str	__a4, [__sp, #12]
	beq	|L..588|
	ldr	__a1, [__sp, #8]
	ldr	__ip, [__a1, #12]
	cmp	__a3, #0
	and	__a3, __ip, #1
	beq	|L..589|
	ldr	__ip, |L..652|+4
	mov	__a3, __a3, asl #7
	ldr	__a4, |L..652|+8
	b	|L..651|
|L..589|
	ldr	__ip, |L..652|+12
	mov	__a3, __a3, asl #7
	ldr	__a4, |L..652|+16
|L..651|
	add	__ip, __a3, __ip
	str	__ip, [__sp, #16]
	add	__a3, __a3, __a4
	str	__a3, [__sp, #20]
	b	|L..591|
|L..588|
	cmp	__a3, #0
	beq	|L..592|
	ldr	__a2, |L..652|+20
	ldr	__a3, |L..652|+24
	str	__a2, [__sp, #16]
	str	__a3, [__sp, #20]
	b	|L..591|
|L..592|
	ldr	__a4, |L..652|+28
	ldr	__v1, |L..652|+32
	str	__a4, [__sp, #16]
	str	__v1, [__sp, #20]
|L..591|
	ldr	__a1, [__sp, #8]
	ldr	__ip, [__a1, #16]
	cmp	__ip, #2
	bne	|L..594|
	mov	__v6, #0
	ldr	__ip, [__a1, #20]
	add	__a2, __a1, #48
	str	__a2, [__sp, #116]
	subs	__ip, __ip, __v6
	movne	__ip, #1
	str	__ip, [__sp, #24]
|L..599|
	ldr	__a3, [__sp, #116]
	ldr	__v1, [__sp, #24]
	ldr	__a4, [__a3, __v6, asl #2]
	add	__ip, __v6, #1
	str	__ip, [__sp, #108]
	cmp	__a4, #3
	movgt	__v1, #0
	cmp	__a4, #11
	str	__v1, [__sp, #24]
	bgt	|L..602|
|L..604|
	mov	__a2, __a4, asl #1
	ldr	__a1, [__sp, #8]
	add	__ip, __a2, __a4
	ldr	__a3, [__a1, #20]
	add	__ip, __ip, __v6
	rsb	__ip, __a3, __ip
	ldr	__a3, [__sp, #4]
	ldr	__a1, [__a3, __ip, asl #2]
	add	__a4, __a4, #1
	str	__a4, [__sp, #112]
	cmp	__a1, #7
	beq	|L..603|
	ldr	__a4, [__sp, #12]
	ldr	__v1, [__sp, #12]
	add	__ip, __a4, #118
	ldr	__a4, [__ip, __a2]	; movhi
	add	__ip, __v1, #90
	ldr	__a3, [__ip, __a2]	; movhi
	mov	__a4, __a4, asl #16
	mov	__a3, __a3, asl #16
	add	__v5, __v6, __a3, asr #16
	mov	__a3, __a1, asl #3
	ldr	__a1, [__sp, #16]
	mov	__v4, __a4, asr #16
	add	__ip, __a3, __a1
	ldmia	__ip, {__a4-__v1}
	add	__a1, __sp, #32
	stmda	__a1, {__a4-__v1}
	ldr	__a2, [__sp, #20]
	cmp	__v4, #0
	add	__a3, __a3, __a2
	ldmia	__a3, {__a4-__v1}
	mov	__ip, __a1
	stmib	__ip, {__a4-__v1}
	ble	|L..603|
|L..609|
	add	__a1, __sp, #32
	ldr	__a2, [__sp, #0]
	sub	__v4, __v4, #1
	ldmda	__a1, {__a3-__a4}
	add	__v3, __a2, __v5, asl #3
	ldmia	__v3, {__v1-__v2}
	add	__v5, __v5, #3
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	stmia	__v3, {__a1-__a2}
	mov	__a2, __v2
	mov	__a1, __v1
	add	__v1, __sp, #32
	ldmib	__v1, {__a3-__a4}
	bl	|__muldf3|
	cmp	__v4, #0
	add	__v3, __v3, #4608
	stmia	__v3, {__a1-__a2}
	bgt	|L..609|
|L..603|
	ldr	__a4, [__sp, #112]
	cmp	__a4, #11
	ble	|L..604|
|L..602|
	ldr	__a1, [__sp, #12]
	ldr	__a2, [__sp, #8]
	ldr	__a4, [__sp, #4]
	ldr	__ip, [__a1, #140]
	ldr	__a3, [__a2, #20]
	mov	__v4, __ip, asr #16
	sub	__a3, __a3, #33
	ldr	__ip, [__a1, #112]
	rsb	__a3, __a3, __v6
	ldr	__a1, [__a4, __a3, asl #2]
	add	__v5, __v6, __ip, asr #16
	cmp	__a1, #7
	beq	|L..598|
	ldr	__v1, [__sp, #16]
	mov	__a3, __a1, asl #3
	add	__ip, __a3, __v1
	ldmia	__ip, {__a4-__v1}
	add	__a1, __sp, #48
	stmda	__a1, {__a4-__v1}
	ldr	__a2, [__sp, #20]
	cmp	__v4, #0
	add	__a3, __a3, __a2
	ldmia	__a3, {__a4-__v1}
	mov	__ip, __a1
	stmib	__ip, {__a4-__v1}
	ble	|L..598|
|L..616|
	add	__a1, __sp, #48
	ldr	__a2, [__sp, #0]
	sub	__v4, __v4, #1
	ldmda	__a1, {__a3-__a4}
	add	__v3, __a2, __v5, asl #3
	ldmia	__v3, {__v1-__v2}
	add	__v5, __v5, #3
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	stmia	__v3, {__a1-__a2}
	mov	__a2, __v2
	mov	__a1, __v1
	add	__v1, __sp, #48
	ldmib	__v1, {__a3-__a4}
	bl	|__muldf3|
	cmp	__v4, #0
	add	__v3, __v3, #4608
	stmia	__v3, {__a1-__a2}
	bgt	|L..616|
|L..598|
	ldr	__v6, [__sp, #108]
	cmp	__v6, #2
	ble	|L..599|
	ldr	__ip, [__sp, #24]
	cmp	__ip, #0
	beq	|L..632|
	ldr	__a1, [__sp, #8]
	ldr	__a2, [__sp, #12]
	ldr	__a4, [__a1, #60]
	ldr	__ip, [__a2, __a4, asl #1]	; movhi
	cmp	__a4, #7
	mov	__ip, __ip, asl #16
	mov	__ip, __ip, asr #16
	str	__ip, [__sp, #60]
	bgt	|L..632|
|L..623|
	ldr	__a3, [__sp, #12]
	ldr	__v1, [__sp, #4]
	add	__ip, __a3, #46
	ldr	__a3, [__ip, __a4, asl #1]	; movhi
	ldr	__ip, [__v1, __a4, asl #2]
	mov	__a3, __a3, asl #16
	mov	__v4, __a3, asr #16
	cmp	__ip, #7
	beq	|L..624|
	add	__a4, __a4, #1
	ldr	__a1, [__sp, #16]
	mov	__a3, __ip, asl #3
	str	__a4, [__sp, #104]
	add	__ip, __a3, __a1
	ldmia	__ip, {__a4-__v1}
	add	__a1, __sp, #64
	stmia	__a1, {__a4-__v1}
	ldr	__a2, [__sp, #20]
	cmp	__v4, #0
	add	__a3, __a3, __a2
	ldmia	__a3, {__v5-__v6}
	ble	|L..622|
|L..628|
	ldr	__ip, [__sp, #0]
	add	__v1, __sp, #64
	ldr	__a1, [__sp, #60]
	sub	__v4, __v4, #1
	ldmia	__v1, {__a3-__a4}
	add	__v3, __ip, __a1, asl #3
	ldmia	__v3, {__v1-__v2}
	add	__a1, __a1, #1
	str	__a1, [__sp, #60]
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	stmia	__v3, {__a1-__a2}
	mov	__a2, __v2
	mov	__a1, __v1
	mov	__a4, __v6
	mov	__a3, __v5
	bl	|__muldf3|
	cmp	__v4, #0
	add	__v3, __v3, #4608
	stmia	__v3, {__a1-__a2}
	bgt	|L..628|
	b	|L..622|
|L..653|
	ALIGN
|L..652|
	DCD	|bandInfo|
	DCD	|pow1_2|
	DCD	|pow2_2|
	DCD	|pow1_1|
	DCD	|pow2_1|
	DCD	|tan1_2|
	DCD	|tan2_2|
	DCD	|tan1_1|
	DCD	|tan2_1|
|L..624|
	ldr	__a2, [__sp, #60]
	add	__a4, __a4, #1
	str	__a4, [__sp, #104]
	add	__a2, __a2, __v4
	str	__a2, [__sp, #60]
|L..622|
	ldr	__a4, [__sp, #104]
	cmp	__a4, #7
	ble	|L..623|
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..594|
	ldr	__a3, [__sp, #8]
	ldr	__v1, [__sp, #12]
	ldr	__a4, [__a3, #60]
	ldr	__ip, [__v1, __a4, asl #1]	; movhi
	cmp	__a4, #20
	mov	__ip, __ip, asl #16
	mov	__v5, __ip, asr #16
	bgt	|L..634|
|L..636|
	ldr	__a1, [__sp, #12]
	ldr	__v1, [__sp, #4]
	add	__ip, __a1, #46
	ldr	__a3, [__ip, __a4, asl #1]	; movhi
	ldr	__a2, [__v1, __a4, asl #2]
	mov	__a3, __a3, asl #16
	mov	__v4, __a3, asr #16
	cmp	__a2, #7
	beq	|L..637|
	add	__v6, __a4, #1
	ldr	__a1, [__sp, #16]
	mov	__a3, __a2, asl #3
	add	__ip, __a3, __a1
	ldmia	__ip, {__a4-__v1}
	add	__a1, __sp, #80
	stmdb	__a1, {__a4-__v1}
	ldr	__a2, [__sp, #20]
	cmp	__v4, #0
	add	__a3, __a3, __a2
	ldmia	__a3, {__a4-__v1}
	mov	__ip, __a1
	stmia	__ip, {__a4-__v1}
	ble	|L..635|
|L..641|
	add	__a1, __sp, #80
	ldr	__a2, [__sp, #0]
	sub	__v4, __v4, #1
	ldmdb	__a1, {__a3-__a4}
	add	__v3, __a2, __v5, asl #3
	ldmia	__v3, {__v1-__v2}
	add	__v5, __v5, #1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	stmia	__v3, {__a1-__a2}
	mov	__a2, __v2
	mov	__a1, __v1
	add	__v1, __sp, #80
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	cmp	__v4, #0
	add	__v3, __v3, #4608
	stmia	__v3, {__a1-__a2}
	bgt	|L..641|
	b	|L..635|
|L..637|
	add	__v5, __v5, __v4
	add	__v6, __a4, #1
|L..635|
	mov	__a4, __v6
	cmp	__a4, #20
	ble	|L..636|
|L..634|
	ldr	__ip, [__sp, #4]
	ldr	__a2, [__ip, #80]
	cmp	__a2, #7
	beq	|L..632|
	ldr	__a1, [__sp, #12]
	add	__a1, __a1, #88
	ldr	__ip, [__a1, #2]	; load-rotate
	mov	__v4, __ip, asr #16
	mov	__ip, __a2, asl #3
	ldr	__a2, [__sp, #16]
	add	__a3, __ip, __a2
	ldmia	__a3, {__a4-__v1}
	add	__a1, __sp, #96
	stmdb	__a1, {__a4-__v1}
	ldr	__a2, [__sp, #20]
	cmp	__v4, #0
	add	__ip, __ip, __a2
	ldmia	__ip, {__a3-__a4}
	mov	__v1, __a1
	stmia	__v1, {__a3-__a4}
	ble	|L..632|
|L..649|
	add	__ip, __sp, #96
	ldr	__a1, [__sp, #0]
	sub	__v4, __v4, #1
	ldmdb	__ip, {__a3-__a4}
	add	__v3, __a1, __v5, asl #3
	ldmia	__v3, {__v1-__v2}
	add	__v5, __v5, #1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	stmia	__v3, {__a1-__a2}
	mov	__a2, __v2
	mov	__a1, __v1
	add	__v1, __sp, #96
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	cmp	__v4, #0
	add	__v3, __v3, #4608
	stmia	__v3, {__a1-__a2}
	bgt	|L..649|
|L..632|
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
	ALIGN
|dct36|
	KEEP |dct36|
	; args = 4, pretend = 0, frame = 672, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	sub	__ip, __sp, #672
	cmp	__ip, __sl
	bllt	|__rt_stkovf_split_big|
	sub	__sp, __sp, #672
	str	__a1, [__sp, #12]
	str	__a2, [__sp, #0]
	add	__a1, __a1, #136
	str	__a1, [__sp, #16]
	ldmia	__a1, {__a1-__a2}
	str	__a3, [__sp, #4]
	ldr	__a3, [__sp, #12]
	str	__a4, [__sp, #8]
	add	__a3, __a3, #128
	str	__a3, [__sp, #20]
	ldmia	__a3, {__a3-__a4}
	bl	|__adddf3|
	ldr	__a4, [__sp, #16]
	stmia	__a4, {__a1-__a2}
	ldr	__v1, [__sp, #20]
	ldr	__v2, [__sp, #12]
	ldmia	__v1, {__a1-__a2}
	add	__v2, __v2, #120
	str	__v2, [__sp, #24]
	ldmia	__v2, {__a3-__a4}
	bl	|__adddf3|
	stmia	__v1, {__a1-__a2}
	ldr	__v3, [__sp, #12]
	ldmia	__v2, {__a1-__a2}
	add	__v3, __v3, #112
	str	__v3, [__sp, #28]
	ldmia	__v3, {__a3-__a4}
	bl	|__adddf3|
	stmia	__v2, {__a1-__a2}
	ldr	__v4, [__sp, #12]
	ldmia	__v3, {__a1-__a2}
	add	__v6, __v4, #104
	ldmia	__v6, {__a3-__a4}
	bl	|__adddf3|
	stmia	__v3, {__a1-__a2}
	ldmia	__v6, {__a1-__a2}
	add	__ip, __v4, #96
	str	__ip, [__sp, #32]
	ldmia	__ip, {__a3-__a4}
	bl	|__adddf3|
	stmia	__v6, {__a1-__a2}
	ldr	__a3, [__sp, #32]
	ldmia	__a3, {__a1-__a2}
	add	__a4, __v4, #88
	str	__a4, [__sp, #36]
	ldmia	__a4, {__a3-__a4}
	bl	|__adddf3|
	ldr	__v1, [__sp, #32]
	stmia	__v1, {__a1-__a2}
	ldr	__v2, [__sp, #36]
	ldmia	__v2, {__a1-__a2}
	add	__v3, __v4, #80
	str	__v3, [__sp, #40]
	ldmia	__v3, {__a3-__a4}
	bl	|__adddf3|
	stmia	__v2, {__a1-__a2}
	ldmia	__v3, {__a1-__a2}
	add	__v4, __v4, #72
	str	__v4, [__sp, #44]
	ldmia	__v4, {__a3-__a4}
	bl	|__adddf3|
	stmia	__v3, {__a1-__a2}
	ldr	__ip, [__sp, #12]
	ldmia	__v4, {__a1-__a2}
	add	__ip, __ip, #64
	str	__ip, [__sp, #48]
	ldmia	__ip, {__a3-__a4}
	bl	|__adddf3|
	stmia	__v4, {__a1-__a2}
	ldr	__a3, [__sp, #48]
	ldr	__a4, [__sp, #12]
	ldmia	__a3, {__a1-__a2}
	add	__a4, __a4, #56
	str	__a4, [__sp, #52]
	ldmia	__a4, {__a3-__a4}
	bl	|__adddf3|
	ldr	__v1, [__sp, #48]
	stmia	__v1, {__a1-__a2}
	ldr	__v2, [__sp, #52]
	ldr	__v3, [__sp, #12]
	ldmia	__v2, {__a1-__a2}
	add	__v2, __v3, #48
	ldmia	__v2, {__a3-__a4}
	bl	|__adddf3|
	ldr	__v4, [__sp, #52]
	stmia	__v4, {__a1-__a2}
	ldmia	__v2, {__a1-__a2}
	add	__ip, __v3, #40
	str	__ip, [__sp, #56]
	ldmia	__ip, {__a3-__a4}
	bl	|__adddf3|
	stmia	__v2, {__a1-__a2}
	ldr	__a3, [__sp, #56]
	ldmia	__a3, {__a1-__a2}
	add	__a4, __v3, #32
	str	__a4, [__sp, #60]
	ldmia	__a4, {__a3-__a4}
	bl	|__adddf3|
	ldr	__v1, [__sp, #56]
	stmia	__v1, {__a1-__a2}
	ldr	__v3, [__sp, #60]
	ldr	__v4, [__sp, #12]
	ldmia	__v3, {__a1-__a2}
	add	__v1, __v4, #24
	ldmia	__v1, {__a3-__a4}
	bl	|__adddf3|
	stmia	__v3, {__a1-__a2}
	ldmia	__v1, {__a1-__a2}
	add	__ip, __v4, #16
	str	__ip, [__sp, #64]
	ldmia	__ip, {__a3-__a4}
	bl	|__adddf3|
	stmia	__v1, {__a1-__a2}
	ldr	__a3, [__sp, #64]
	ldmia	__a3, {__a1-__a2}
	add	__a4, __v4, #8
	str	__a4, [__sp, #68]
	ldmia	__a4, {__a3-__a4}
	bl	|__adddf3|
	ldr	__v3, [__sp, #64]
	stmia	__v3, {__a1-__a2}
	ldr	__v4, [__sp, #68]
	ldr	__ip, [__sp, #12]
	ldmia	__v4, {__a1-__a2}
	ldmia	__ip, {__a3-__a4}
	bl	|__adddf3|
	stmia	__v4, {__a1-__a2}
	ldr	__a3, [__sp, #16]
	ldr	__v3, [__sp, #24]
	ldmia	__a3, {__a1-__a2}
	ldmia	__v3, {__a3-__a4}
	bl	|__adddf3|
	ldr	__v4, [__sp, #16]
	stmia	__v4, {__a1-__a2}
	ldmia	__v3, {__a1-__a2}
	ldmia	__v6, {__a3-__a4}
	bl	|__adddf3|
	stmia	__v3, {__a1-__a2}
	ldr	__ip, [__sp, #36]
	ldmia	__v6, {__a1-__a2}
	ldmia	__ip, {__a3-__a4}
	bl	|__adddf3|
	stmia	__v6, {__a1-__a2}
	ldr	__a3, [__sp, #36]
	ldr	__v3, [__sp, #44]
	ldmia	__a3, {__a1-__a2}
	ldmia	__v3, {__a3-__a4}
	bl	|__adddf3|
	ldr	__v4, [__sp, #36]
	stmia	__v4, {__a1-__a2}
	ldr	__ip, [__sp, #52]
	ldmia	__v3, {__a1-__a2}
	ldmia	__ip, {__a3-__a4}
	bl	|__adddf3|
	stmia	__v3, {__a1-__a2}
	ldr	__a3, [__sp, #52]
	ldr	__v3, [__sp, #56]
	ldmia	__a3, {__a1-__a2}
	ldmia	__v3, {__a3-__a4}
	bl	|__adddf3|
	ldr	__v4, [__sp, #52]
	stmia	__v4, {__a1-__a2}
	ldmia	__v3, {__a1-__a2}
	ldmia	__v1, {__a3-__a4}
	bl	|__adddf3|
	stmia	__v3, {__a1-__a2}
	ldr	__ip, [__sp, #68]
	ldmia	__v1, {__a1-__a2}
	ldmia	__ip, {__a3-__a4}
	bl	|__adddf3|
	add	__a3, __sp, #80
	stmdb	__a3, {__a1-__a2}
	stmia	__v1, {__a1-__a2}
	ldr	__v3, |L..670|
	ldmia	__v3, {__v3-__v4}
	add	__ip, __sp, #672
	stmdb	__ip, {__v3-__v4}
	ldmia	__v2, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	ldr	__v4, [__fp, #4]
	str	__v4, [__sp, #88]
	bl	|__muldf3|
	add	__ip, __sp, #128
	stmda	__ip, {__a1-__a2}
	ldr	__a1, [__sp, #32]
	ldmia	__a1, {__a1-__a2}
	mov	__a3, __ip
	stmib	__a3, {__a1-__a2}
	ldr	__a2, |L..670|+4
	mov	__v3, __ip
	ldmia	__a2, {__v1-__v2}
	add	__ip, __sp, #96
	ldmib	__a3, {__a1-__a2}
	ldmda	__v3, {__v3-__v4}
	mov	__a4, __v2
	mov	__a3, __v1
	stmda	__ip, {__v3-__v4}
	bl	|__muldf3|
	add	__v4, __sp, #672
	ldmdb	__v4, {__a3-__a4}
	ldr	__ip, [__sp, #52]
	mov	__v4, __a2
	mov	__v3, __a1
	ldmia	__ip, {__a1-__a2}
	add	__ip, __sp, #96
	stmib	__ip, {__v3-__v4}
	bl	|__muldf3|
	mov	__a4, __v2
	mov	__a3, __v1
	ldmia	__v6, {__v1-__v2}
	add	__v3, __sp, #144
	stmda	__v3, {__v1-__v2}
	add	__v4, __sp, #112
	mov	__v2, __a2
	mov	__v1, __a1
	ldmda	__v3, {__a1-__a2}
	stmda	__v4, {__v1-__v2}
	bl	|__muldf3|
	mov	__v2, __a2
	mov	__v1, __a1
	ldr	__a1, [__sp, #64]
	ldmia	__a1, {__a1-__a2}
	add	__a3, __sp, #144
	stmib	__a3, {__a1-__a2}
	ldr	__a2, |L..670|+8
	ldmia	__a2, {__a2-__a3}
	add	__a4, __sp, #608
	stmdb	__a4, {__a2-__a3}
	add	__v3, __sp, #112
	add	__a3, __sp, #144
	ldmib	__a3, {__a1-__a2}
	ldmdb	__a4, {__a3-__a4}
	stmib	__v3, {__v1-__v2}
	bl	|__muldf3|
	add	__v4, __sp, #96
	ldmda	__v4, {__a3-__a4}
	bl	|__adddf3|
	mov	__v2, __a2
	mov	__v1, __a1
	ldr	__a1, [__sp, #40]
	ldmia	__a1, {__a1-__a2}
	add	__a3, __sp, #160
	stmda	__a3, {__a1-__a2}
	ldr	__a2, |L..670|+12
	ldmia	__a2, {__a2-__a3}
	add	__a4, __sp, #608
	stmia	__a4, {__a2-__a3}
	add	__a3, __sp, #160
	ldmda	__a3, {__a1-__a2}
	ldmia	__a4, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__adddf3|
	ldr	__v3, [__sp, #28]
	ldmia	__v3, {__v3-__v4}
	add	__ip, __sp, #160
	stmib	__ip, {__v3-__v4}
	mov	__v2, __a2
	mov	__v1, __a1
	ldr	__ip, |L..670|+16
	add	__a3, __sp, #160
	ldmia	__ip, {__v3-__v4}
	ldmib	__a3, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__adddf3|
	add	__a4, __sp, #176
	stmda	__a4, {__a1-__a2}
	add	__v1, __sp, #80
	ldmdb	__v1, {__a1-__a2}
	add	__v2, __sp, #608
	ldmdb	__v2, {__a3-__a4}
	bl	|__muldf3|
	add	__ip, __sp, #112
	ldmda	__ip, {__a3-__a4}
	bl	|__adddf3|
	add	__v1, __sp, #608
	ldmia	__v1, {__a3-__a4}
	ldr	__v1, [__sp, #36]
	ldmia	__v1, {__v1-__v2}
	add	__ip, __sp, #176
	stmib	__ip, {__v1-__v2}
	mov	__v2, __a2
	mov	__v1, __a1
	ldmib	__ip, {__a1-__a2}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__adddf3|
	ldr	__v2, [__sp, #24]
	mov	__a4, __v4
	mov	__a3, __v3
	ldmia	__v2, {__v2-__v3}
	add	__v4, __sp, #192
	stmda	__v4, {__v2-__v3}
	mov	__v2, __a2
	mov	__v1, __a1
	ldmda	__v4, {__a1-__a2}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__adddf3|
	add	__v3, __sp, #192
	stmib	__v3, {__a1-__a2}
	ldr	__a1, [__sp, #60]
	ldmia	__a1, {__a1-__a2}
	add	__a3, __sp, #208
	stmda	__a3, {__a1-__a2}
	ldr	__a2, |L..670|+20
	ldmia	__a2, {__a2-__a3}
	add	__a4, __sp, #624
	stmdb	__a4, {__a2-__a3}
	add	__a3, __sp, #208
	ldmda	__a3, {__a1-__a2}
	ldmdb	__a4, {__a3-__a4}
	bl	|__muldf3|
	ldr	__v1, [__sp, #12]
	ldmia	__v1, {__v1-__v2}
	add	__v3, __sp, #208
	stmib	__v3, {__v1-__v2}
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__adddf3|
	ldr	__v3, [__sp, #48]
	ldmia	__v3, {__v3-__v4}
	add	__ip, __sp, #224
	stmda	__ip, {__v3-__v4}
	mov	__v2, __a2
	mov	__v1, __a1
	ldr	__a1, |L..670|+24
	ldmia	__a1, {__a1-__a2}
	add	__a3, __sp, #624
	stmia	__a3, {__a1-__a2}
	ldmda	__ip, {__a1-__a2}
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__adddf3|
	add	__v1, __sp, #96
	ldmib	__v1, {__a3-__a4}
	bl	|__adddf3|
	ldr	__v3, [__sp, #20]
	b	|L..669|
|L..671|
	ALIGN
|L..670|
	DCD	|COS9|+24
	DCD	|COS9|+48
	DCD	|COS9|+8
	DCD	|COS9|+40
	DCD	|COS9|+56
	DCD	|COS9|+16
	DCD	|COS9|+32
|L..669|
	ldmia	__v3, {__v3-__v4}
	add	__ip, __sp, #224
	stmib	__ip, {__v3-__v4}
	mov	__v2, __a2
	mov	__v1, __a1
	ldr	__ip, |L..673|
	add	__a3, __sp, #224
	ldmia	__ip, {__v3-__v4}
	ldmib	__a3, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__adddf3|
	add	__v1, __sp, #624
	ldmdb	__v1, {__a3-__a4}
	ldr	__v1, [__sp, #56]
	ldmia	__v1, {__v1-__v2}
	add	__ip, __sp, #240
	stmib	__ip, {__v1-__v2}
	stmda	__ip, {__a1-__a2}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	ldr	__a1, [__sp, #68]
	ldmia	__a1, {__a1-__a2}
	add	__v1, __sp, #256
	stmda	__v1, {__a1-__a2}
	bl	|__adddf3|
	add	__v1, __sp, #624
	ldmia	__v1, {__a3-__a4}
	ldr	__v1, [__sp, #44]
	ldmia	__v1, {__v1-__v2}
	add	__ip, __sp, #256
	stmib	__ip, {__v1-__v2}
	mov	__v2, __a2
	mov	__v1, __a1
	ldmib	__ip, {__a1-__a2}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__adddf3|
	add	__v2, __sp, #112
	ldmib	__v2, {__a3-__a4}
	bl	|__adddf3|
	mov	__a4, __v4
	mov	__a3, __v3
	ldr	__v3, [__sp, #16]
	ldmia	__v3, {__v3-__v4}
	add	__ip, __sp, #272
	stmda	__ip, {__v3-__v4}
	mov	__v2, __a2
	mov	__v1, __a1
	mov	__a2, __v4
	mov	__a1, __v3
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__adddf3|
	add	__v4, __sp, #272
	stmib	__v4, {__a1-__a2}
	add	__ip, __sp, #176
	ldmda	__ip, {__a1-__a2}
	add	__v1, __sp, #240
	ldmda	__v1, {__a3-__a4}
	bl	|__adddf3|
	add	__v2, __sp, #288
	stmda	__v2, {__a1-__a2}
	add	__v3, __sp, #192
	ldmib	__v3, {__a1-__a2}
	add	__v4, __sp, #272
	ldmib	__v4, {__a3-__a4}
	bl	|__adddf3|
	ldr	__ip, |L..673|+4
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__v4, __a2
	mov	__v3, __a1
	add	__a3, __sp, #288
	ldmda	__a3, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__adddf3|
	ldr	__v6, [__sp, #8]
	mov	__v2, __a2
	mov	__v1, __a1
	add	__ip, __v6, #216
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	ldr	__a4, [__sp, #4]
	str	__a4, [__sp, #80]
	add	__ip, __a4, #72
	stmia	__ip, {__a1-__a2}
	add	__a2, __v6, #208
	ldmia	__a2, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	ldr	__v1, [__sp, #80]
	add	__ip, __v1, #64
	stmia	__ip, {__a1-__a2}
	add	__v2, __sp, #288
	mov	__a4, __v4
	mov	__a3, __v3
	ldmda	__v2, {__a1-__a2}
	bl	|__subdf3|
	add	__ip, __v6, #64
	mov	__v2, __a2
	mov	__v1, __a1
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	ldr	__v3, [__sp, #0]
	str	__v3, [__sp, #84]
	mov	__a4, __a2
	mov	__a3, __a1
	add	__ip, __v3, #64
	ldmia	__ip, {__a1-__a2}
	bl	|__adddf3|
	ldr	__v4, [__sp, #88]
	add	__ip, __v4, #2048
	stmia	__ip, {__a1-__a2}
	add	__a2, __v6, #72
	ldmia	__a2, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	ldr	__a3, [__sp, #84]
	add	__ip, __a3, #72
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__ip, {__a1-__a2}
	bl	|__adddf3|
	add	__ip, __v4, #2304
	stmia	__ip, {__a1-__a2}
	add	__a4, __sp, #240
	ldmda	__a4, {__a1-__a2}
	add	__v1, __sp, #176
	ldmda	__v1, {__a3-__a4}
	bl	|__subdf3|
	add	__v2, __sp, #288
	stmib	__v2, {__a1-__a2}
	add	__v3, __sp, #272
	ldmib	__v3, {__a1-__a2}
	add	__v4, __sp, #192
	ldmib	__v4, {__a3-__a4}
	bl	|__subdf3|
	ldr	__ip, |L..673|+4
	add	__a3, __ip, #64
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	mov	__v4, __a2
	mov	__v3, __a1
	add	__a3, __sp, #288
	ldmib	__a3, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__adddf3|
	add	__ip, __v6, #280
	mov	__v2, __a2
	mov	__v1, __a1
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	ldr	__a4, [__sp, #80]
	add	__ip, __a4, #136
	stmia	__ip, {__a1-__a2}
	add	__a2, __v6, #144
	ldmia	__a2, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	ldr	__v1, [__sp, #80]
	stmia	__v1, {__a1-__a2}
	add	__v2, __sp, #288
	mov	__a4, __v4
	mov	__a3, __v3
	ldmib	__v2, {__a1-__a2}
	bl	|__subdf3|
	mov	__v2, __a2
	mov	__v1, __a1
	ldmia	__v6, {__a3-__a4}
	bl	|__muldf3|
	ldr	__v3, [__sp, #84]
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__v3, {__a1-__a2}
	bl	|__adddf3|
	ldr	__v4, [__sp, #88]
	stmia	__v4, {__a1-__a2}
	add	__ip, __v6, #136
	ldmia	__ip, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	add	__ip, __v3, #136
	b	|L..672|
|L..674|
	ALIGN
|L..673|
	DCD	|COS9|+64
	DCD	|tfcos36|
|L..672|
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__ip, {__a1-__a2}
	bl	|__adddf3|
	add	__ip, __v4, #4352
	stmia	__ip, {__a1-__a2}
	add	__ip, __sp, #144
	ldmib	__ip, {__a1-__a2}
	add	__v1, __sp, #160
	ldmda	__v1, {__a3-__a4}
	bl	|__subdf3|
	add	__v2, __sp, #160
	ldmib	__v2, {__a3-__a4}
	bl	|__subdf3|
	ldr	__v3, |L..676|
	ldmia	__v3, {__v1-__v2}
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__muldf3|
	add	__v4, __sp, #304
	stmda	__v4, {__a1-__a2}
	add	__ip, __sp, #80
	ldmdb	__ip, {__a1-__a2}
	add	__v3, __sp, #176
	ldmib	__v3, {__a3-__a4}
	bl	|__subdf3|
	add	__v4, __sp, #192
	ldmda	__v4, {__a3-__a4}
	bl	|__subdf3|
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__muldf3|
	add	__ip, __sp, #304
	stmib	__ip, {__a1-__a2}
	add	__a3, __sp, #208
	ldmda	__a3, {__a1-__a2}
	add	__v1, __sp, #224
	ldmda	__v1, {__a3-__a4}
	bl	|__subdf3|
	add	__v2, __sp, #224
	ldmib	__v2, {__a3-__a4}
	bl	|__subdf3|
	ldr	__v3, |L..676|+4
	ldmia	__v3, {__v1-__v2}
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__muldf3|
	add	__v4, __sp, #128
	ldmib	__v4, {__a3-__a4}
	bl	|__subdf3|
	add	__ip, __sp, #208
	ldmib	__ip, {__a3-__a4}
	bl	|__adddf3|
	add	__a3, __sp, #320
	stmda	__a3, {__a1-__a2}
	add	__a4, __sp, #240
	ldmib	__a4, {__a1-__a2}
	add	__v3, __sp, #256
	ldmib	__v3, {__a3-__a4}
	bl	|__subdf3|
	add	__v4, __sp, #272
	ldmda	__v4, {__a3-__a4}
	bl	|__subdf3|
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__muldf3|
	add	__ip, __sp, #144
	ldmda	__ip, {__a3-__a4}
	bl	|__subdf3|
	add	__v1, __sp, #256
	ldmda	__v1, {__a3-__a4}
	bl	|__adddf3|
	add	__v2, __sp, #320
	stmib	__v2, {__a1-__a2}
	add	__v3, __sp, #304
	ldmda	__v3, {__a1-__a2}
	ldmda	__v2, {__a3-__a4}
	bl	|__adddf3|
	add	__v4, __sp, #336
	stmda	__v4, {__a1-__a2}
	add	__ip, __sp, #304
	ldmib	__ip, {__a1-__a2}
	add	__v1, __sp, #320
	ldmib	__v1, {__a3-__a4}
	bl	|__adddf3|
	ldr	__v2, |L..676|+8
	add	__ip, __v2, #8
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__v4, __a2
	mov	__v3, __a1
	add	__ip, __sp, #336
	ldmda	__ip, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__adddf3|
	add	__ip, __v6, #224
	mov	__v2, __a2
	mov	__v1, __a1
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	ldr	__a3, [__sp, #80]
	add	__ip, __a3, #80
	stmia	__ip, {__a1-__a2}
	add	__a2, __v6, #200
	ldmia	__a2, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	ldr	__a4, [__sp, #80]
	add	__ip, __a4, #56
	stmia	__ip, {__a1-__a2}
	add	__v1, __sp, #336
	ldmda	__v1, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__subdf3|
	add	__ip, __v6, #56
	mov	__v2, __a2
	mov	__v1, __a1
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	ldr	__v3, [__sp, #84]
	mov	__a4, __a2
	mov	__a3, __a1
	add	__ip, __v3, #56
	ldmia	__ip, {__a1-__a2}
	bl	|__adddf3|
	ldr	__v4, [__sp, #88]
	add	__ip, __v4, #1792
	stmia	__ip, {__a1-__a2}
	add	__a2, __v6, #80
	ldmia	__a2, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	add	__ip, __v3, #80
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__ip, {__a1-__a2}
	bl	|__adddf3|
	add	__ip, __v4, #2560
	stmia	__ip, {__a1-__a2}
	add	__ip, __sp, #320
	ldmda	__ip, {__a1-__a2}
	add	__v1, __sp, #304
	ldmda	__v1, {__a3-__a4}
	bl	|__subdf3|
	add	__v2, __sp, #336
	stmib	__v2, {__a1-__a2}
	add	__v3, __sp, #320
	ldmib	__v3, {__a1-__a2}
	add	__v4, __sp, #304
	ldmib	__v4, {__a3-__a4}
	bl	|__subdf3|
	ldr	__ip, |L..676|+8
	add	__a3, __ip, #56
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	mov	__v4, __a2
	mov	__v3, __a1
	add	__a3, __sp, #336
	ldmib	__a3, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__adddf3|
	add	__ip, __v6, #272
	mov	__v2, __a2
	mov	__v1, __a1
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	ldr	__a4, [__sp, #80]
	add	__ip, __a4, #128
	stmia	__ip, {__a1-__a2}
	add	__a2, __v6, #152
	ldmia	__a2, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	ldr	__v1, [__sp, #80]
	add	__ip, __v1, #8
	stmia	__ip, {__a1-__a2}
	add	__v2, __sp, #336
	mov	__a4, __v4
	mov	__a3, __v3
	ldmib	__v2, {__a1-__a2}
	bl	|__subdf3|
	add	__ip, __v6, #8
	mov	__v2, __a2
	mov	__v1, __a1
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	ldr	__v3, [__sp, #84]
	mov	__a4, __a2
	mov	__a3, __a1
	add	__ip, __v3, #8
	ldmia	__ip, {__a1-__a2}
	bl	|__adddf3|
	ldr	__v4, [__sp, #88]
	add	__ip, __v4, #256
	stmia	__ip, {__a1-__a2}
	add	__a2, __v6, #128
	ldmia	__a2, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	add	__ip, __v3, #128
	mov	__a4, __a2
	mov	__a3, __a1
	b	|L..675|
|L..677|
	ALIGN
|L..676|
	DCD	|COS9|+24
	DCD	|COS9|+48
	DCD	|tfcos36|
|L..675|
	ldmia	__ip, {__a1-__a2}
	bl	|__adddf3|
	add	__ip, __v4, #4096
	stmia	__ip, {__a1-__a2}
	add	__a1, __sp, #144
	ldmib	__a1, {__a1-__a2}
	add	__a3, __sp, #352
	stmda	__a3, {__a1-__a2}
	ldr	__a2, |L..679|
	ldmia	__a2, {__a2-__a3}
	add	__a4, __sp, #640
	stmdb	__a4, {__a2-__a3}
	add	__a3, __sp, #352
	ldmda	__a3, {__a1-__a2}
	ldmdb	__a4, {__a3-__a4}
	bl	|__muldf3|
	add	__v1, __sp, #96
	ldmda	__v1, {__a3-__a4}
	bl	|__subdf3|
	add	__v3, __sp, #160
	ldmda	__v3, {__v3-__v4}
	add	__ip, __sp, #352
	stmib	__ip, {__v3-__v4}
	mov	__v2, __a2
	mov	__v1, __a1
	ldr	__a1, |L..679|+4
	ldmia	__a1, {__a1-__a2}
	add	__a3, __sp, #640
	stmia	__a3, {__a1-__a2}
	ldmib	__ip, {__a1-__a2}
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__subdf3|
	mov	__v2, __a2
	mov	__v1, __a1
	add	__a2, __sp, #160
	ldmib	__a2, {__a2-__a3}
	add	__a4, __sp, #368
	stmda	__a4, {__a2-__a3}
	ldr	__a3, |L..679|+8
	ldmia	__a3, {__v3-__v4}
	ldmda	__a4, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__adddf3|
	add	__a4, __sp, #368
	stmib	__a4, {__a1-__a2}
	add	__v1, __sp, #80
	ldmdb	__v1, {__v1-__v2}
	add	__ip, __sp, #384
	stmda	__ip, {__v1-__v2}
	mov	__a2, __v2
	mov	__a1, __v1
	add	__v2, __sp, #640
	ldmdb	__v2, {__a3-__a4}
	bl	|__muldf3|
	add	__ip, __sp, #112
	ldmda	__ip, {__a3-__a4}
	bl	|__subdf3|
	mov	__v2, __a2
	mov	__v1, __a1
	add	__a1, __sp, #176
	ldmib	__a1, {__a1-__a2}
	add	__a3, __sp, #384
	stmib	__a3, {__a1-__a2}
	add	__ip, __sp, #640
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__subdf3|
	mov	__v2, __a2
	mov	__v1, __a1
	add	__a1, __sp, #192
	ldmda	__a1, {__a1-__a2}
	add	__a3, __sp, #400
	stmda	__a3, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__adddf3|
	add	__a3, __sp, #400
	stmib	__a3, {__a1-__a2}
	add	__a4, __sp, #208
	ldmda	__a4, {__a4-__v1}
	add	__v2, __sp, #416
	stmda	__v2, {__a4-__v1}
	ldr	__v1, |L..679|+12
	ldmia	__v1, {__v1-__v2}
	add	__v3, __sp, #656
	stmdb	__v3, {__v1-__v2}
	add	__v2, __sp, #416
	ldmda	__v2, {__a1-__a2}
	ldmdb	__v3, {__a3-__a4}
	bl	|__muldf3|
	add	__v3, __sp, #208
	ldmib	__v3, {__v3-__v4}
	add	__ip, __sp, #416
	stmib	__ip, {__v3-__v4}
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v4
	mov	__a1, __v3
	bl	|__subdf3|
	mov	__v2, __a2
	mov	__v1, __a1
	add	__a1, __sp, #224
	ldmda	__a1, {__a1-__a2}
	add	__a3, __sp, #432
	stmda	__a3, {__a1-__a2}
	ldr	__a2, |L..679|+16
	ldmia	__a2, {__a2-__a3}
	add	__a4, __sp, #656
	stmia	__a4, {__a2-__a3}
	add	__a3, __sp, #432
	ldmda	__a3, {__a1-__a2}
	ldmia	__a4, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__subdf3|
	add	__v1, __sp, #96
	ldmib	__v1, {__a3-__a4}
	bl	|__adddf3|
	add	__v3, __sp, #224
	ldmib	__v3, {__v3-__v4}
	add	__ip, __sp, #432
	stmib	__ip, {__v3-__v4}
	mov	__v2, __a2
	mov	__v1, __a1
	ldr	__ip, |L..679|+20
	add	__a3, __sp, #432
	ldmia	__ip, {__v3-__v4}
	ldmib	__a3, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__adddf3|
	add	__a4, __sp, #448
	stmda	__a4, {__a1-__a2}
	add	__v1, __sp, #240
	ldmib	__v1, {__v1-__v2}
	mov	__ip, __a4
	stmib	__ip, {__v1-__v2}
	mov	__a2, __v2
	mov	__a1, __v1
	add	__v2, __sp, #656
	ldmdb	__v2, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	add	__a1, __sp, #256
	ldmda	__a1, {__a1-__a2}
	add	__v1, __sp, #464
	stmda	__v1, {__a1-__a2}
	bl	|__subdf3|
	mov	__v2, __a2
	mov	__v1, __a1
	add	__a2, __sp, #256
	ldmib	__a2, {__a2-__a3}
	add	__a4, __sp, #464
	stmib	__a4, {__a2-__a3}
	add	__ip, __sp, #656
	mov	__a1, __a2
	mov	__a2, __a3
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__subdf3|
	add	__v1, __sp, #112
	ldmib	__v1, {__a3-__a4}
	bl	|__adddf3|
	mov	__v2, __a2
	mov	__v1, __a1
	add	__a1, __sp, #272
	ldmda	__a1, {__a1-__a2}
	add	__a3, __sp, #480
	b	|L..678|
|L..680|
	ALIGN
|L..679|
	DCD	|COS9|+40
	DCD	|COS9|+56
	DCD	|COS9|+8
	DCD	|COS9|+64
	DCD	|COS9|+16
	DCD	|COS9|+32
|L..678|
	stmda	__a3, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__adddf3|
	add	__a3, __sp, #480
	stmib	__a3, {__a1-__a2}
	add	__a4, __sp, #368
	ldmib	__a4, {__a1-__a2}
	add	__v1, __sp, #448
	ldmda	__v1, {__a3-__a4}
	bl	|__adddf3|
	add	__v2, __sp, #496
	stmda	__v2, {__a1-__a2}
	add	__v3, __sp, #400
	ldmib	__v3, {__a1-__a2}
	add	__v4, __sp, #480
	ldmib	__v4, {__a3-__a4}
	bl	|__adddf3|
	ldr	__a3, |L..682|
	add	__ip, __a3, #16
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__v4, __a2
	mov	__v3, __a1
	add	__a4, __sp, #496
	ldmda	__a4, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__adddf3|
	add	__ip, __v6, #232
	mov	__v2, __a2
	mov	__v1, __a1
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	ldr	__a3, [__sp, #80]
	add	__ip, __a3, #88
	stmia	__ip, {__a1-__a2}
	add	__a2, __v6, #192
	ldmia	__a2, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	ldr	__a4, [__sp, #80]
	add	__ip, __a4, #48
	stmia	__ip, {__a1-__a2}
	add	__v1, __sp, #496
	ldmda	__v1, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__subdf3|
	add	__ip, __v6, #48
	mov	__v2, __a2
	mov	__v1, __a1
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	ldr	__v3, [__sp, #84]
	mov	__a4, __a2
	mov	__a3, __a1
	add	__ip, __v3, #48
	ldmia	__ip, {__a1-__a2}
	bl	|__adddf3|
	ldr	__v4, [__sp, #88]
	add	__ip, __v4, #1536
	stmia	__ip, {__a1-__a2}
	add	__a2, __v6, #88
	ldmia	__a2, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	add	__ip, __v3, #88
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__ip, {__a1-__a2}
	bl	|__adddf3|
	add	__ip, __v4, #2816
	stmia	__ip, {__a1-__a2}
	add	__ip, __sp, #448
	ldmda	__ip, {__a1-__a2}
	add	__v1, __sp, #368
	ldmib	__v1, {__a3-__a4}
	bl	|__subdf3|
	add	__v2, __sp, #496
	stmib	__v2, {__a1-__a2}
	add	__v3, __sp, #480
	ldmib	__v3, {__a1-__a2}
	add	__v4, __sp, #400
	ldmib	__v4, {__a3-__a4}
	bl	|__subdf3|
	ldr	__ip, |L..682|
	add	__a3, __ip, #48
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	mov	__v4, __a2
	mov	__v3, __a1
	add	__a3, __sp, #496
	ldmib	__a3, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__adddf3|
	add	__ip, __v6, #264
	mov	__v2, __a2
	mov	__v1, __a1
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	ldr	__a4, [__sp, #80]
	add	__ip, __a4, #120
	stmia	__ip, {__a1-__a2}
	add	__a2, __v6, #160
	ldmia	__a2, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	ldr	__v1, [__sp, #80]
	add	__ip, __v1, #16
	stmia	__ip, {__a1-__a2}
	add	__v2, __sp, #496
	mov	__a4, __v4
	mov	__a3, __v3
	ldmib	__v2, {__a1-__a2}
	bl	|__subdf3|
	add	__ip, __v6, #16
	mov	__v2, __a2
	mov	__v1, __a1
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	ldr	__v3, [__sp, #84]
	mov	__a4, __a2
	mov	__a3, __a1
	add	__ip, __v3, #16
	ldmia	__ip, {__a1-__a2}
	bl	|__adddf3|
	ldr	__v4, [__sp, #88]
	add	__ip, __v4, #512
	stmia	__ip, {__a1-__a2}
	add	__a2, __v6, #120
	ldmia	__a2, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	add	__ip, __v3, #120
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__ip, {__a1-__a2}
	bl	|__adddf3|
	add	__ip, __v4, #3840
	stmia	__ip, {__a1-__a2}
	ldr	__a1, |L..682|+4
	ldmia	__a1, {__a1-__a2}
	add	__a3, __sp, #512
	stmda	__a3, {__a1-__a2}
	add	__v1, __sp, #512
	add	__a3, __sp, #352
	ldmda	__a3, {__a1-__a2}
	ldmda	__v1, {__a3-__a4}
	bl	|__muldf3|
	add	__v2, __sp, #96
	ldmda	__v2, {__a3-__a4}
	bl	|__subdf3|
	ldr	__v3, |L..682|+8
	ldmia	__v3, {__v3-__v4}
	add	__ip, __sp, #512
	stmib	__ip, {__v3-__v4}
	mov	__v2, __a2
	mov	__v1, __a1
	add	__v4, __sp, #352
	ldmib	__v4, {__a1-__a2}
	ldmib	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__adddf3|
	mov	__v2, __a2
	mov	__v1, __a1
	ldr	__ip, |L..682|+12
	ldmia	__ip, {__v3-__v4}
	add	__a3, __sp, #368
	ldmda	__a3, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__subdf3|
	add	__a4, __sp, #528
	stmda	__a4, {__a1-__a2}
	add	__v1, __sp, #384
	ldmda	__v1, {__a1-__a2}
	add	__v2, __sp, #512
	ldmda	__v2, {__a3-__a4}
	bl	|__muldf3|
	add	__ip, __sp, #112
	ldmda	__ip, {__a3-__a4}
	bl	|__subdf3|
	mov	__v2, __a2
	mov	__v1, __a1
	add	__a3, __sp, #384
	ldmib	__a3, {__a1-__a2}
	add	__ip, __sp, #512
	ldmib	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__adddf3|
	mov	__v2, __a2
	mov	__v1, __a1
	add	__a3, __sp, #400
	ldmda	__a3, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	b	|L..681|
|L..683|
	ALIGN
|L..682|
	DCD	|tfcos36|
	DCD	|COS9|+56
	DCD	|COS9|+8
	DCD	|COS9|+40
|L..681|
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__subdf3|
	add	__a4, __sp, #528
	stmib	__a4, {__a1-__a2}
	ldr	__v1, |L..685|
	ldmia	__v1, {__v1-__v2}
	add	__v3, __sp, #544
	stmda	__v3, {__v1-__v2}
	add	__v2, __sp, #416
	ldmda	__v2, {__a1-__a2}
	ldmda	__v3, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	add	__v3, __sp, #416
	ldmib	__v3, {__a1-__a2}
	bl	|__subdf3|
	mov	__v2, __a2
	mov	__v1, __a1
	ldr	__a1, |L..685|+4
	ldmia	__a1, {__a1-__a2}
	add	__a3, __sp, #544
	stmib	__a3, {__a1-__a2}
	add	__v3, __sp, #544
	add	__a3, __sp, #432
	ldmda	__a3, {__a1-__a2}
	ldmib	__v3, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__adddf3|
	add	__v4, __sp, #96
	ldmib	__v4, {__a3-__a4}
	bl	|__adddf3|
	mov	__v2, __a2
	mov	__v1, __a1
	ldr	__ip, |L..685|+8
	ldmia	__ip, {__v3-__v4}
	add	__a3, __sp, #432
	ldmib	__a3, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__subdf3|
	add	__a4, __sp, #560
	stmda	__a4, {__a1-__a2}
	add	__v1, __sp, #448
	ldmib	__v1, {__a1-__a2}
	add	__v2, __sp, #544
	ldmda	__v2, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	add	__ip, __sp, #464
	ldmda	__ip, {__a1-__a2}
	bl	|__subdf3|
	mov	__v2, __a2
	mov	__v1, __a1
	add	__a3, __sp, #464
	ldmib	__a3, {__a1-__a2}
	add	__ip, __sp, #544
	ldmib	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__adddf3|
	add	__v1, __sp, #112
	ldmib	__v1, {__a3-__a4}
	bl	|__adddf3|
	mov	__v2, __a2
	mov	__v1, __a1
	add	__ip, __sp, #480
	ldmda	__ip, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__subdf3|
	add	__a3, __sp, #560
	stmib	__a3, {__a1-__a2}
	add	__a4, __sp, #528
	ldmda	__a4, {__a1-__a2}
	ldmda	__a3, {__a3-__a4}
	bl	|__adddf3|
	add	__v1, __sp, #576
	stmda	__v1, {__a1-__a2}
	add	__v2, __sp, #528
	ldmib	__v2, {__a1-__a2}
	add	__v3, __sp, #560
	ldmib	__v3, {__a3-__a4}
	bl	|__adddf3|
	ldr	__v4, |L..685|+12
	add	__ip, __v4, #24
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__v4, __a2
	mov	__v3, __a1
	add	__ip, __sp, #576
	ldmda	__ip, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__adddf3|
	add	__ip, __v6, #240
	mov	__v2, __a2
	mov	__v1, __a1
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	ldr	__a3, [__sp, #80]
	add	__ip, __a3, #96
	stmia	__ip, {__a1-__a2}
	add	__a2, __v6, #184
	ldmia	__a2, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	ldr	__a4, [__sp, #80]
	add	__ip, __a4, #40
	stmia	__ip, {__a1-__a2}
	add	__v1, __sp, #576
	ldmda	__v1, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__subdf3|
	add	__ip, __v6, #40
	mov	__v2, __a2
	mov	__v1, __a1
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	ldr	__v3, [__sp, #84]
	mov	__a4, __a2
	mov	__a3, __a1
	add	__ip, __v3, #40
	ldmia	__ip, {__a1-__a2}
	bl	|__adddf3|
	ldr	__v4, [__sp, #88]
	add	__ip, __v4, #1280
	stmia	__ip, {__a1-__a2}
	add	__a2, __v6, #96
	ldmia	__a2, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	add	__ip, __v3, #96
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__ip, {__a1-__a2}
	bl	|__adddf3|
	add	__ip, __v4, #3072
	stmia	__ip, {__a1-__a2}
	add	__ip, __sp, #560
	ldmda	__ip, {__a1-__a2}
	add	__v1, __sp, #528
	ldmda	__v1, {__a3-__a4}
	bl	|__subdf3|
	add	__v2, __sp, #576
	stmib	__v2, {__a1-__a2}
	add	__v3, __sp, #560
	ldmib	__v3, {__a1-__a2}
	add	__v4, __sp, #528
	ldmib	__v4, {__a3-__a4}
	bl	|__subdf3|
	ldr	__ip, |L..685|+12
	add	__a3, __ip, #40
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	mov	__v4, __a2
	mov	__v3, __a1
	add	__a3, __sp, #576
	ldmib	__a3, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__adddf3|
	add	__ip, __v6, #256
	mov	__v2, __a2
	mov	__v1, __a1
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	ldr	__a4, [__sp, #80]
	add	__ip, __a4, #112
	stmia	__ip, {__a1-__a2}
	add	__a2, __v6, #168
	ldmia	__a2, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	ldr	__v1, [__sp, #80]
	add	__ip, __v1, #24
	stmia	__ip, {__a1-__a2}
	add	__v2, __sp, #576
	mov	__a4, __v4
	mov	__a3, __v3
	b	|L..684|
|L..686|
	ALIGN
|L..685|
	DCD	|COS9|+32
	DCD	|COS9|+64
	DCD	|COS9|+16
	DCD	|tfcos36|
|L..684|
	ldmib	__v2, {__a1-__a2}
	bl	|__subdf3|
	add	__ip, __v6, #24
	mov	__v2, __a2
	mov	__v1, __a1
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	ldr	__v3, [__sp, #84]
	mov	__a4, __a2
	mov	__a3, __a1
	add	__ip, __v3, #24
	ldmia	__ip, {__a1-__a2}
	bl	|__adddf3|
	ldr	__v4, [__sp, #88]
	add	__ip, __v4, #768
	stmia	__ip, {__a1-__a2}
	add	__a2, __v6, #112
	ldmia	__a2, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	add	__ip, __v3, #112
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__ip, {__a1-__a2}
	bl	|__adddf3|
	add	__ip, __v4, #3584
	stmia	__ip, {__a1-__a2}
	add	__ip, __sp, #416
	ldmib	__ip, {__a1-__a2}
	ldmda	__ip, {__a3-__a4}
	bl	|__subdf3|
	add	__v1, __sp, #432
	ldmda	__v1, {__a3-__a4}
	bl	|__adddf3|
	ldr	__v2, [__sp, #12]
	add	__v2, __v2, #96
	str	__v2, [__sp, #588]
	ldmia	__v2, {__a3-__a4}
	bl	|__subdf3|
	add	__v3, __sp, #432
	ldmib	__v3, {__a3-__a4}
	bl	|__adddf3|
	add	__v4, __sp, #592
	stmia	__v4, {__a1-__a2}
	add	__ip, __sp, #464
	ldmda	__ip, {__a1-__a2}
	add	__v1, __sp, #448
	ldmib	__v1, {__a3-__a4}
	bl	|__subdf3|
	add	__v2, __sp, #464
	ldmib	__v2, {__a3-__a4}
	bl	|__adddf3|
	ldr	__v3, [__sp, #12]
	add	__a3, __v3, #104
	ldmia	__a3, {__a3-__a4}
	bl	|__subdf3|
	add	__v4, __sp, #480
	ldmda	__v4, {__a3-__a4}
	bl	|__adddf3|
	ldr	__ip, |L..687|
	mov	__v5, #32
	add	__a3, __ip, __v5
	ldmia	__a3, {__a3-__a4}
	bl	|__muldf3|
	mov	__v4, __a2
	mov	__v3, __a1
	add	__a3, __sp, #592
	ldmia	__a3, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__adddf3|
	add	__ip, __v6, #248
	mov	__v2, __a2
	mov	__v1, __a1
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	ldr	__a4, [__sp, #80]
	add	__ip, __a4, #104
	stmia	__ip, {__a1-__a2}
	add	__a2, __v6, #176
	ldmia	__a2, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	ldr	__v1, [__sp, #80]
	add	__a3, __v1, __v5
	stmia	__a3, {__a1-__a2}
	add	__v2, __sp, #592
	ldmia	__v2, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__subdf3|
	add	__ip, __v6, __v5
	mov	__v2, __a2
	mov	__v1, __a1
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	ldr	__v3, [__sp, #84]
	mov	__a4, __a2
	mov	__a3, __a1
	add	__ip, __v3, __v5
	ldmia	__ip, {__a1-__a2}
	bl	|__adddf3|
	ldr	__v4, [__sp, #88]
	add	__ip, __v4, #1024
	stmia	__ip, {__a1-__a2}
	add	__a2, __v6, #104
	ldmia	__a2, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	add	__ip, __v3, #104
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__ip, {__a1-__a2}
	bl	|__adddf3|
	add	__ip, __v4, #3328
	stmia	__ip, {__a1-__a2}
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..688|
	ALIGN
|L..687|
	DCD	|tfcos36|
	ALIGN
|dct12|
	KEEP |dct12|
	; args = 4, pretend = 0, frame = 436, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	sub	__ip, __sp, #436
	cmp	__ip, __sl
	bllt	|__rt_stkovf_split_big|
	sub	__sp, __sp, #436
	str	__a1, [__sp, #0]
	mov	__v5, __a2
	ldr	__v6, [__fp, #4]
	add	__ip, __a1, #120
	ldmia	__ip, {__a1-__a2}
	mov	__ip, __v5
	ldmia	__ip!, {__v1-__v2}
	stmia	__v6, {__v1-__v2}
	ldmia	__ip, {__v2-__v3}
	add	__lr, __v6, #256
	stmia	__lr, {__v2-__v3}
	add	__ip, __v5, #16
	ldmia	__ip, {__v2-__v3}
	add	__v1, __v6, #512
	stmia	__v1, {__v2-__v3}
	add	__ip, __v5, #24
	ldmia	__ip, {__v1-__v2}
	add	__lr, __v6, #768
	stmia	__lr, {__v1-__v2}
	add	__ip, __v5, #32
	ldmia	__ip, {__v2-__v3}
	add	__v1, __v6, #1024
	stmia	__v1, {__v2-__v3}
	add	__ip, __v5, #40
	ldmia	__ip, {__v1-__v2}
	add	__lr, __v6, #1280
	stmia	__lr, {__v1-__v2}
	ldr	__v2, [__sp, #0]
	str	__a3, [__sp, #4]
	add	__ip, __v2, #96
	ldmia	__ip, {__v1-__v2}
	str	__a4, [__sp, #8]
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__adddf3|
	add	__v3, __sp, #32
	stmda	__v3, {__a1-__a2}
	ldr	__lr, [__sp, #0]
	add	__v3, __sp, #16
	add	__ip, __lr, #72
	ldmia	__ip, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	stmib	__v3, {__a3-__a4}
	bl	|__adddf3|
	add	__ip, __sp, #32
	stmib	__ip, {__a1-__a2}
	ldr	__lr, [__sp, #0]
	add	__ip, __lr, #48
	ldmia	__ip, {__v3-__v4}
	add	__a3, __sp, #16
	ldmib	__a3, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__adddf3|
	add	__a4, __sp, #48
	stmda	__a4, {__a1-__a2}
	ldr	__v1, [__sp, #0]
	add	__ip, __v1, #24
	ldmia	__ip, {__v1-__v2}
	mov	__a2, __v4
	mov	__a1, __v3
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__adddf3|
	ldr	__lr, [__sp, #0]
	ldmia	__lr!, {__a3-__a4}
	add	__ip, __sp, #16
	stmda	__ip, {__a3-__a4}
	mov	__v4, __a2
	mov	__v3, __a1
	str	__lr, [__sp, #0]
	mov	__a2, __v2
	mov	__a1, __v1
	ldmda	__ip, {__a3-__a4}
	bl	|__adddf3|
	add	__a3, __sp, #48
	stmib	__a3, {__a1-__a2}
	add	__a4, __sp, #32
	ldmda	__a4, {__a1-__a2}
	ldmda	__a3, {__a3-__a4}
	bl	|__adddf3|
	add	__v1, __sp, #64
	stmda	__v1, {__a1-__a2}
	add	__v2, __sp, #48
	ldmda	__v2, {__a1-__a2}
	ldmib	__v2, {__a3-__a4}
	bl	|__adddf3|
	mov	__v2, __a2
	mov	__v1, __a1
	ldr	__a2, |L..691|
	ldmia	__a2, {__a2-__a3}
	add	__a4, __sp, #64
	stmib	__a4, {__a2-__a3}
	mov	__a2, __v4
	mov	__a1, __v3
	ldmib	__a4, {__a3-__a4}
	bl	|__muldf3|
	add	__a3, __sp, #80
	stmda	__a3, {__a1-__a2}
	mov	__a2, __v2
	mov	__a1, __v1
	add	__v1, __sp, #64
	ldmib	__v1, {__a3-__a4}
	bl	|__muldf3|
	add	__v2, __sp, #80
	stmib	__v2, {__a1-__a2}
	add	__v3, __sp, #16
	ldmda	__v3, {__a1-__a2}
	add	__ip, __sp, #32
	ldmib	__ip, {__a3-__a4}
	bl	|__subdf3|
	mov	__v4, __a2
	mov	__v3, __a1
	add	__lr, __sp, #48
	ldmib	__lr, {__a1-__a2}
	add	__v1, __sp, #64
	ldmda	__v1, {__a3-__a4}
	bl	|__subdf3|
	ldr	__v2, |L..691|+4
	ldmia	__v2, {__a3-__a4}
	bl	|__muldf3|
	mov	__v2, __a2
	mov	__v1, __a1
	mov	__a2, __v4
	mov	__a1, __v3
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__adddf3|
	add	__ip, __sp, #96
	stmda	__ip, {__a1-__a2}
	mov	__a2, __v4
	mov	__a1, __v3
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__subdf3|
	mov	__v3, __a2
	mov	__v2, __a1
	ldr	__a3, [__sp, #8]
	add	__lr, __sp, #96
	ldmda	__lr, {__a1-__a2}
	add	__a3, __a3, #80
	str	__a3, [__sp, #104]
	ldmia	__a3, {__a3-__a4}
	add	__v1, __v6, #4096
	str	__v1, [__sp, #100]
	bl	|__muldf3|
	add	__ip, __v5, #128
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__ip, {__a1-__a2}
	bl	|__adddf3|
	stmia	__v1, {__a1-__a2}
	ldr	__lr, [__sp, #8]
	add	__ip, __sp, #96
	ldmda	__ip, {__a1-__a2}
	add	__lr, __lr, #56
	str	__lr, [__sp, #112]
	ldmia	__lr, {__a3-__a4}
	add	__v1, __v6, #3328
	str	__v1, [__sp, #108]
	bl	|__muldf3|
	add	__ip, __v5, #104
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__ip, {__a1-__a2}
	bl	|__adddf3|
	stmia	__v1, {__a1-__a2}
	ldr	__ip, [__sp, #8]
	add	__ip, __ip, #8
	str	__ip, [__sp, #116]
	mov	__a2, __v3
	mov	__a1, __v2
	ldmia	__ip, {__a3-__a4}
	add	__v1, __v6, #1792
	bl	|__muldf3|
	add	__ip, __v5, #56
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__ip, {__a1-__a2}
	bl	|__adddf3|
	stmia	__v1, {__a1-__a2}
	ldr	__lr, [__sp, #8]
	add	__lr, __lr, #32
	str	__lr, [__sp, #120]
	mov	__a2, __v3
	mov	__a1, __v2
	ldmia	__lr, {__a3-__a4}
	add	__v1, __v6, #2560
	bl	|__muldf3|
	add	__ip, __v5, #80
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__ip, {__a1-__a2}
	bl	|__adddf3|
	stmia	__v1, {__a1-__a2}
	ldr	__a2, |L..691|+8
	ldmia	__a2, {__a2-__a3}
	add	__a4, __sp, #128
	stmda	__a4, {__a2-__a3}
	add	__a3, __sp, #32
	ldmib	__a3, {__a1-__a2}
	ldmda	__a4, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	add	__v1, __sp, #16
	ldmda	__v1, {__a1-__a2}
	bl	|__adddf3|
	mov	__v2, __a2
	mov	__v1, __a1
	add	__v3, __sp, #80
	ldmda	__v3, {__a3-__a4}
	bl	|__adddf3|
	add	__ip, __sp, #128
	stmib	__ip, {__a1-__a2}
	mov	__a2, __v2
	mov	__a1, __v1
	add	__lr, __sp, #80
	ldmda	__lr, {__a3-__a4}
	bl	|__subdf3|
	add	__a3, __sp, #144
	stmda	__a3, {__a1-__a2}
	add	__a4, __sp, #64
	ldmda	__a4, {__a1-__a2}
	add	__v1, __sp, #128
	ldmda	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	add	__v2, __sp, #48
	ldmib	__v2, {__a1-__a2}
	bl	|__adddf3|
	mov	__v2, __a2
	mov	__v1, __a1
	add	__v3, __sp, #80
	ldmib	__v3, {__a3-__a4}
	bl	|__adddf3|
	ldr	__ip, |L..691|+12
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__v4, __a2
	mov	__v3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	add	__lr, __sp, #80
	ldmib	__lr, {__a3-__a4}
	bl	|__subdf3|
	ldr	__v1, |L..691|+16
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__v2, __a2
	mov	__v1, __a1
	add	__ip, __sp, #128
	ldmib	__ip, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__adddf3|
	add	__lr, __sp, #144
	stmib	__lr, {__a1-__a2}
	add	__a3, __sp, #128
	ldmib	__a3, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__subdf3|
	add	__a4, __sp, #160
	stmda	__a4, {__a1-__a2}
	add	__v3, __sp, #144
	ldmda	__v3, {__a1-__a2}
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__adddf3|
	mov	__v4, __a2
	mov	__v3, __a1
	add	__ip, __sp, #144
	ldmda	__ip, {__a1-__a2}
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__subdf3|
	add	__lr, __sp, #160
	stmib	__lr, {__a1-__a2}
	ldr	__a3, [__sp, #8]
	add	__a3, __a3, #88
	str	__a3, [__sp, #176]
	mov	__a2, __v4
	mov	__a1, __v3
	ldmia	__a3, {__a3-__a4}
	add	__v1, __v6, #4352
	str	__v1, [__sp, #172]
	b	|L..690|
|L..692|
	ALIGN
|L..691|
	DCD	|COS6_1|
	DCD	|tfcos12|+8
	DCD	|COS6_2|
	DCD	|tfcos12|
	DCD	|tfcos12|+16
|L..690|
	bl	|__muldf3|
	add	__ip, __v5, #136
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__ip, {__a1-__a2}
	bl	|__adddf3|
	stmia	__v1, {__a1-__a2}
	ldr	__v2, [__sp, #8]
	add	__v2, __v2, #48
	str	__v2, [__sp, #184]
	mov	__a2, __v4
	mov	__a1, __v3
	ldmia	__v2, {__a3-__a4}
	add	__v3, __v6, #3072
	str	__v3, [__sp, #180]
	bl	|__muldf3|
	add	__ip, __v5, #96
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__ip, {__a1-__a2}
	bl	|__adddf3|
	stmia	__v3, {__a1-__a2}
	ldr	__lr, [__sp, #8]
	add	__ip, __sp, #144
	ldmib	__ip, {__a1-__a2}
	add	__lr, __lr, #64
	str	__lr, [__sp, #192]
	ldmia	__lr, {__a3-__a4}
	add	__v1, __v6, #3584
	str	__v1, [__sp, #188]
	bl	|__muldf3|
	add	__ip, __v5, #112
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__ip, {__a1-__a2}
	bl	|__adddf3|
	stmia	__v1, {__a1-__a2}
	ldr	__v3, [__sp, #8]
	add	__v2, __sp, #144
	ldmib	__v2, {__a1-__a2}
	add	__v3, __v3, #72
	str	__v3, [__sp, #200]
	ldmia	__v3, {__a3-__a4}
	add	__ip, __v6, #3840
	str	__ip, [__sp, #196]
	bl	|__muldf3|
	add	__ip, __v5, #120
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__ip, {__a1-__a2}
	bl	|__adddf3|
	ldr	__lr, [__sp, #196]
	stmia	__lr, {__a1-__a2}
	add	__a3, __sp, #160
	ldmib	__a3, {__a1-__a2}
	ldr	__v1, [__sp, #8]
	ldmia	__v1, {__a3-__a4}
	add	__v1, __v6, #1536
	bl	|__muldf3|
	add	__ip, __v5, #48
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__ip, {__a1-__a2}
	bl	|__adddf3|
	stmia	__v1, {__a1-__a2}
	ldr	__v3, [__sp, #8]
	add	__v2, __sp, #160
	ldmib	__v2, {__a1-__a2}
	add	__v3, __v3, #40
	str	__v3, [__sp, #204]
	ldmia	__v3, {__a3-__a4}
	add	__v1, __v6, #2816
	bl	|__muldf3|
	add	__ip, __v5, #88
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__ip, {__a1-__a2}
	bl	|__adddf3|
	stmia	__v1, {__a1-__a2}
	ldr	__lr, [__sp, #8]
	add	__ip, __sp, #160
	ldmda	__ip, {__a1-__a2}
	add	__lr, __lr, #16
	str	__lr, [__sp, #208]
	ldmia	__lr, {__a3-__a4}
	add	__v1, __v6, #2048
	bl	|__muldf3|
	add	__ip, __v5, #64
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__ip, {__a1-__a2}
	bl	|__adddf3|
	stmia	__v1, {__a1-__a2}
	ldr	__a4, [__sp, #8]
	add	__a3, __sp, #160
	ldmda	__a3, {__a1-__a2}
	add	__a4, __a4, #24
	str	__a4, [__sp, #212]
	ldmia	__a4, {__a3-__a4}
	add	__v1, __v6, #2304
	bl	|__muldf3|
	add	__v5, __v5, #72
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__v5, {__a1-__a2}
	bl	|__adddf3|
	stmia	__v1, {__a1-__a2}
	ldr	__v1, [__sp, #0]
	add	__ip, __v1, #96
	ldmia	__ip, {__v3-__v4}
	add	__a3, __v1, #120
	ldmia	__a3, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__adddf3|
	add	__v2, __sp, #224
	stmia	__v2, {__a1-__a2}
	add	__ip, __v1, #72
	ldmia	__ip, {__v1-__v2}
	mov	__a2, __v4
	mov	__a1, __v3
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__adddf3|
	add	__v3, __sp, #240
	stmdb	__v3, {__a1-__a2}
	ldr	__lr, [__sp, #0]
	add	__ip, __lr, #48
	ldmia	__ip, {__v3-__v4}
	mov	__a2, __v2
	mov	__a1, __v1
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__adddf3|
	mov	__v6, __a2
	mov	__v5, __a1
	ldr	__a2, [__sp, #0]
	add	__ip, __a2, #24
	ldmia	__ip, {__v1-__v2}
	mov	__a2, __v4
	mov	__a1, __v3
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__adddf3|
	ldr	__lr, [__sp, #0]
	ldmia	__lr!, {__a3-__a4}
	add	__ip, __sp, #224
	stmdb	__ip, {__a3-__a4}
	mov	__v4, __a2
	mov	__v3, __a1
	str	__lr, [__sp, #0]
	mov	__a2, __v2
	mov	__a1, __v1
	ldmdb	__ip, {__a3-__a4}
	bl	|__adddf3|
	add	__a3, __sp, #240
	stmia	__a3, {__a1-__a2}
	add	__a4, __sp, #224
	ldmia	__a4, {__a1-__a2}
	mov	__a4, __v6
	mov	__a3, __v5
	bl	|__adddf3|
	add	__v1, __sp, #256
	stmdb	__v1, {__a1-__a2}
	mov	__a2, __v6
	mov	__a1, __v5
	add	__v2, __sp, #240
	ldmia	__v2, {__a3-__a4}
	bl	|__adddf3|
	mov	__v2, __a2
	mov	__v1, __a1
	mov	__a2, __v4
	mov	__a1, __v3
	add	__v3, __sp, #64
	ldmib	__v3, {__a3-__a4}
	bl	|__muldf3|
	add	__ip, __sp, #256
	stmia	__ip, {__a1-__a2}
	mov	__a2, __v2
	mov	__a1, __v1
	add	__lr, __sp, #64
	ldmib	__lr, {__a3-__a4}
	bl	|__muldf3|
	add	__a3, __sp, #272
	stmdb	__a3, {__a1-__a2}
	add	__a4, __sp, #224
	ldmdb	__a4, {__a1-__a2}
	add	__v1, __sp, #240
	ldmdb	__v1, {__a3-__a4}
	bl	|__subdf3|
	mov	__v6, __a2
	mov	__v5, __a1
	add	__v2, __sp, #240
	ldmia	__v2, {__a1-__a2}
	add	__v3, __sp, #256
	ldmdb	__v3, {__a3-__a4}
	bl	|__subdf3|
	ldr	__ip, |L..694|
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__v2, __a2
	mov	__v1, __a1
	mov	__a2, __v6
	mov	__a1, __v5
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__adddf3|
	mov	__v4, __a2
	mov	__v3, __a1
	mov	__a2, __v6
	mov	__a1, __v5
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__subdf3|
	ldr	__lr, [__sp, #104]
	mov	__v2, __a2
	mov	__v1, __a1
	ldmia	__lr, {__a3-__a4}
	mov	__a2, __v4
	mov	__a1, __v3
	bl	|__muldf3|
	ldr	__a3, [__sp, #4]
	add	__a3, __a3, #32
	str	__a3, [__sp, #272]
	stmia	__a3, {__a1-__a2}
	ldr	__ip, [__sp, #112]
	ldmia	__ip, {__a3-__a4}
	mov	__a2, __v4
	mov	__a1, __v3
	bl	|__muldf3|
	ldr	__lr, [__sp, #4]
	add	__lr, __lr, #8
	str	__lr, [__sp, #276]
	stmia	__lr, {__a1-__a2}
	ldr	__a2, [__sp, #116]
	ldmia	__a2, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	ldr	__v3, [__sp, #108]
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__v3, {__a1-__a2}
	bl	|__adddf3|
	stmia	__v3, {__a1-__a2}
	ldr	__ip, [__sp, #120]
	ldmia	__ip, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	ldr	__lr, [__sp, #100]
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__lr, {__a1-__a2}
	bl	|__adddf3|
	ldr	__a3, [__sp, #100]
	stmia	__a3, {__a1-__a2}
	add	__a4, __sp, #240
	add	__v1, __sp, #128
	ldmdb	__a4, {__a1-__a2}
	ldmda	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	add	__v2, __sp, #224
	ldmdb	__v2, {__a1-__a2}
	bl	|__adddf3|
	mov	__v2, __a2
	mov	__v1, __a1
	add	__v3, __sp, #256
	ldmia	__v3, {__a3-__a4}
	bl	|__adddf3|
	add	__ip, __sp, #288
	stmdb	__ip, {__a1-__a2}
	mov	__a2, __v2
	mov	__a1, __v1
	add	__lr, __sp, #256
	ldmia	__lr, {__a3-__a4}
	bl	|__subdf3|
	add	__a3, __sp, #288
	stmia	__a3, {__a1-__a2}
	add	__a4, __sp, #256
	ldmdb	__a4, {__a1-__a2}
	add	__v1, __sp, #128
	ldmda	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	add	__v2, __sp, #240
	ldmia	__v2, {__a1-__a2}
	bl	|__adddf3|
	mov	__v2, __a2
	mov	__v1, __a1
	add	__v3, __sp, #272
	ldmdb	__v3, {__a3-__a4}
	bl	|__adddf3|
	ldr	__ip, |L..694|+4
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__v4, __a2
	mov	__v3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	add	__lr, __sp, #272
	ldmdb	__lr, {__a3-__a4}
	bl	|__subdf3|
	ldr	__v1, |L..694|+8
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	mov	__v6, __a2
	mov	__v5, __a1
	add	__v2, __sp, #288
	ldmdb	__v2, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__adddf3|
	add	__ip, __sp, #304
	stmdb	__ip, {__a1-__a2}
	add	__lr, __sp, #288
	ldmdb	__lr, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__subdf3|
	add	__a3, __sp, #304
	stmia	__a3, {__a1-__a2}
	add	__a4, __sp, #288
	ldmia	__a4, {__a1-__a2}
	mov	__a4, __v6
	mov	__a3, __v5
	bl	|__adddf3|
	mov	__v2, __a2
	mov	__v1, __a1
	add	__v3, __sp, #288
	ldmia	__v3, {__a1-__a2}
	mov	__a4, __v6
	mov	__a3, __v5
	bl	|__subdf3|
	ldr	__ip, [__sp, #176]
	mov	__v4, __a2
	mov	__v3, __a1
	ldmia	__ip, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	ldr	__lr, [__sp, #4]
	add	__lr, __lr, #40
	str	__lr, [__sp, #312]
	stmia	__lr, {__a1-__a2}
	ldr	__a2, [__sp, #184]
	ldmia	__a2, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	ldr	__a3, [__sp, #4]
	stmia	__a3, {__a1-__a2}
	ldr	__v1, [__sp, #192]
	add	__v2, __sp, #304
	ldmdb	__v2, {__a1-__a2}
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	ldr	__ip, [__sp, #4]
	add	__v6, __ip, #16
	stmia	__v6, {__a1-__a2}
	ldr	__lr, [__sp, #200]
	add	__v1, __sp, #304
	ldmdb	__v1, {__a1-__a2}
	ldmia	__lr, {__a3-__a4}
	bl	|__muldf3|
	ldr	__v2, [__sp, #4]
	add	__v5, __v2, #24
	stmia	__v5, {__a1-__a2}
	ldr	__ip, [__sp, #8]
	ldmia	__ip, {__a3-__a4}
	mov	__a2, __v4
	mov	__a1, __v3
	bl	|__muldf3|
	ldr	__lr, [__sp, #180]
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__lr, {__a1-__a2}
	bl	|__adddf3|
	ldr	__a3, [__sp, #180]
	stmia	__a3, {__a1-__a2}
	ldr	__v1, [__sp, #204]
	ldmia	__v1, {__a3-__a4}
	mov	__a2, __v4
	mov	__a1, __v3
	bl	|__muldf3|
	ldr	__v2, [__sp, #172]
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__v2, {__a1-__a2}
	bl	|__adddf3|
	stmia	__v2, {__a1-__a2}
	ldr	__v3, [__sp, #208]
	add	__ip, __sp, #304
	ldmia	__ip, {__a1-__a2}
	b	|L..693|
|L..695|
	ALIGN
|L..694|
	DCD	|tfcos12|+8
	DCD	|tfcos12|
	DCD	|tfcos12|+16
|L..693|
	ldmia	__v3, {__a3-__a4}
	bl	|__muldf3|
	ldr	__lr, [__sp, #188]
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__lr, {__a1-__a2}
	bl	|__adddf3|
	ldr	__a3, [__sp, #188]
	stmia	__a3, {__a1-__a2}
	ldr	__v1, [__sp, #212]
	add	__v2, __sp, #304
	ldmia	__v2, {__a1-__a2}
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	ldr	__v3, [__sp, #196]
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__v3, {__a1-__a2}
	bl	|__adddf3|
	stmia	__v3, {__a1-__a2}
	ldr	__lr, [__sp, #4]
	adr	__v1, |L..697|
	ldmia	__v1, {__v1-__v2}
	add	__ip, __lr, #136
	stmia	__ip, {__v1-__v2}
	add	__ip, __lr, #128
	stmia	__ip, {__v1-__v2}
	add	__ip, __lr, #120
	stmia	__ip, {__v1-__v2}
	add	__ip, __lr, #112
	stmia	__ip, {__v1-__v2}
	ldr	__a2, [__sp, #0]
	ldr	__a3, [__sp, #0]
	add	__a1, __a2, #120
	ldmia	__a1, {__a1-__a2}
	add	__ip, __a3, #96
	ldmia	__ip, {__v3-__v4}
	add	__ip, __lr, #104
	stmia	__ip, {__v1-__v2}
	add	__ip, __lr, #96
	stmia	__ip, {__v1-__v2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__adddf3|
	add	__a4, __sp, #320
	stmib	__a4, {__a1-__a2}
	ldr	__v1, [__sp, #0]
	add	__ip, __v1, #72
	ldmia	__ip, {__v1-__v2}
	mov	__a2, __v4
	mov	__a1, __v3
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__adddf3|
	add	__v3, __sp, #336
	stmda	__v3, {__a1-__a2}
	ldr	__lr, [__sp, #0]
	add	__ip, __lr, #48
	ldmia	__ip, {__v3-__v4}
	mov	__a2, __v2
	mov	__a1, __v1
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__adddf3|
	add	__a3, __sp, #336
	stmib	__a3, {__a1-__a2}
	ldr	__a4, [__sp, #0]
	add	__v1, __a4, #24
	ldmia	__v1, {__v1-__v2}
	mov	__a2, __v4
	mov	__a1, __v3
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__adddf3|
	add	__v3, __sp, #352
	stmda	__v3, {__a1-__a2}
	ldr	__a2, [__sp, #0]
	ldmia	__a2, {__a2-__a3}
	add	__a4, __sp, #320
	stmda	__a4, {__a2-__a3}
	mov	__a2, __v2
	mov	__a1, __v1
	ldmda	__a4, {__a3-__a4}
	bl	|__adddf3|
	add	__a3, __sp, #352
	stmib	__a3, {__a1-__a2}
	add	__a4, __sp, #320
	ldmib	__a4, {__a1-__a2}
	add	__v1, __sp, #336
	ldmib	__v1, {__a3-__a4}
	bl	|__adddf3|
	add	__v2, __sp, #368
	stmda	__v2, {__a1-__a2}
	add	__v3, __sp, #336
	ldmib	__v3, {__a1-__a2}
	add	__ip, __sp, #352
	ldmib	__ip, {__a3-__a4}
	bl	|__adddf3|
	mov	__v4, __a2
	mov	__v3, __a1
	ldr	__lr, |L..697|+8
	ldmia	__lr, {__v1-__v2}
	add	__a3, __sp, #352
	ldmda	__a3, {__a1-__a2}
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__muldf3|
	add	__a4, __sp, #368
	stmib	__a4, {__a1-__a2}
	mov	__a2, __v4
	mov	__a1, __v3
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__muldf3|
	add	__v1, __sp, #384
	stmda	__v1, {__a1-__a2}
	add	__v2, __sp, #320
	ldmda	__v2, {__a1-__a2}
	add	__v3, __sp, #336
	ldmda	__v3, {__a3-__a4}
	bl	|__subdf3|
	add	__ip, __sp, #384
	stmib	__ip, {__a1-__a2}
	add	__lr, __sp, #352
	ldmib	__lr, {__a1-__a2}
	add	__v1, __sp, #368
	ldmda	__v1, {__a3-__a4}
	bl	|__subdf3|
	ldr	__v2, |L..697|+12
	ldmia	__v2, {__a3-__a4}
	bl	|__muldf3|
	mov	__v2, __a2
	mov	__v1, __a1
	add	__v3, __sp, #384
	ldmib	__v3, {__a1-__a2}
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__adddf3|
	mov	__v4, __a2
	mov	__v3, __a1
	add	__ip, __sp, #384
	ldmib	__ip, {__a1-__a2}
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__subdf3|
	ldr	__lr, [__sp, #104]
	mov	__v2, __a2
	mov	__v1, __a1
	ldmia	__lr, {__a3-__a4}
	mov	__a2, __v4
	mov	__a1, __v3
	bl	|__muldf3|
	ldr	__a3, [__sp, #4]
	add	__ip, __a3, #80
	stmia	__ip, {__a1-__a2}
	ldr	__ip, [__sp, #112]
	ldmia	__ip, {__a3-__a4}
	mov	__a2, __v4
	mov	__a1, __v3
	bl	|__muldf3|
	ldr	__lr, [__sp, #4]
	add	__ip, __lr, #56
	stmia	__ip, {__a1-__a2}
	ldr	__a2, [__sp, #116]
	ldmia	__a2, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	ldr	__v3, [__sp, #276]
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__v3, {__a1-__a2}
	bl	|__adddf3|
	stmia	__v3, {__a1-__a2}
	ldr	__ip, [__sp, #120]
	ldmia	__ip, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	ldr	__lr, [__sp, #272]
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__lr, {__a1-__a2}
	bl	|__adddf3|
	ldr	__a3, [__sp, #272]
	stmia	__a3, {__a1-__a2}
	ldr	__a4, |L..697|+16
	add	__v1, __sp, #336
	ldmia	__a4, {__v3-__v4}
	ldmda	__v1, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	add	__v2, __sp, #320
	ldmda	__v2, {__a1-__a2}
	bl	|__adddf3|
	mov	__v2, __a2
	mov	__v1, __a1
	add	__ip, __sp, #368
	ldmib	__ip, {__a3-__a4}
	bl	|__adddf3|
	add	__lr, __sp, #400
	stmda	__lr, {__a1-__a2}
	mov	__a2, __v2
	mov	__a1, __v1
	add	__v1, __sp, #368
	ldmib	__v1, {__a3-__a4}
	bl	|__subdf3|
	add	__v2, __sp, #400
	stmib	__v2, {__a1-__a2}
	add	__ip, __sp, #368
	ldmda	__ip, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	b	|L..696|
|L..698|
	ALIGN
|L..697|
	DCD &0, &0	; double 0.00000000000000000000e0
	DCD	|COS6_1|
	DCD	|tfcos12|+8
	DCD	|COS6_2|
|L..696|
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	add	__lr, __sp, #352
	ldmib	__lr, {__a1-__a2}
	bl	|__adddf3|
	mov	__v2, __a2
	mov	__v1, __a1
	add	__v3, __sp, #384
	ldmda	__v3, {__a3-__a4}
	bl	|__adddf3|
	ldr	__ip, |L..699|
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	mov	__v4, __a2
	mov	__v3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	add	__lr, __sp, #384
	ldmda	__lr, {__a3-__a4}
	bl	|__subdf3|
	ldr	__v1, |L..699|+4
	ldmia	__v1, {__a3-__a4}
	bl	|__muldf3|
	add	__v2, __sp, #416
	stmda	__v2, {__a1-__a2}
	add	__ip, __sp, #400
	ldmda	__ip, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__adddf3|
	add	__lr, __sp, #416
	stmib	__lr, {__a1-__a2}
	add	__a3, __sp, #400
	ldmda	__a3, {__a1-__a2}
	mov	__a4, __v4
	mov	__a3, __v3
	bl	|__subdf3|
	add	__a4, __sp, #432
	stmda	__a4, {__a1-__a2}
	add	__v1, __sp, #400
	ldmib	__v1, {__a1-__a2}
	add	__v2, __sp, #416
	ldmda	__v2, {__a3-__a4}
	bl	|__adddf3|
	mov	__v2, __a2
	mov	__v1, __a1
	add	__v3, __sp, #400
	ldmib	__v3, {__a1-__a2}
	add	__ip, __sp, #416
	ldmda	__ip, {__a3-__a4}
	bl	|__subdf3|
	ldr	__lr, [__sp, #176]
	mov	__v4, __a2
	mov	__v3, __a1
	ldmia	__lr, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	ldr	__a3, [__sp, #4]
	add	__ip, __a3, #88
	stmia	__ip, {__a1-__a2}
	ldr	__ip, [__sp, #184]
	ldmia	__ip, {__a3-__a4}
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__muldf3|
	ldr	__lr, [__sp, #4]
	add	__ip, __lr, #48
	stmia	__ip, {__a1-__a2}
	ldr	__a2, [__sp, #192]
	ldmia	__a2, {__a3-__a4}
	add	__v1, __sp, #416
	ldmib	__v1, {__a1-__a2}
	bl	|__muldf3|
	ldr	__v2, [__sp, #4]
	add	__ip, __v2, #64
	stmia	__ip, {__a1-__a2}
	ldr	__ip, [__sp, #200]
	add	__lr, __sp, #416
	ldmib	__lr, {__a1-__a2}
	ldmia	__ip, {__a3-__a4}
	bl	|__muldf3|
	add	__ip, __v2, #72
	stmia	__ip, {__a1-__a2}
	ldr	__a2, [__sp, #8]
	ldmia	__a2, {__a3-__a4}
	mov	__a2, __v4
	mov	__a1, __v3
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__v2, {__a1-__a2}
	bl	|__adddf3|
	stmia	__v2, {__a1-__a2}
	ldr	__v1, [__sp, #204]
	ldmia	__v1, {__a3-__a4}
	mov	__a2, __v4
	mov	__a1, __v3
	bl	|__muldf3|
	ldr	__v2, [__sp, #312]
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__v2, {__a1-__a2}
	bl	|__adddf3|
	stmia	__v2, {__a1-__a2}
	ldr	__v3, [__sp, #208]
	add	__ip, __sp, #432
	ldmda	__ip, {__a1-__a2}
	ldmia	__v3, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__v6, {__a1-__a2}
	bl	|__adddf3|
	stmia	__v6, {__a1-__a2}
	ldr	__lr, [__sp, #212]
	add	__v1, __sp, #432
	ldmda	__v1, {__a1-__a2}
	ldmia	__lr, {__a3-__a4}
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	ldmia	__v5, {__a1-__a2}
	bl	|__adddf3|
	stmia	__v5, {__a1-__a2}
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..700|
	ALIGN
|L..699|
	DCD	|tfcos12|
	DCD	|tfcos12|+16
	ALIGN
|III_hybrid|
	KEEP |III_hybrid|
	; args = 4, pretend = 0, frame = 8, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	bllt	|__rt_stkovf_split_small|
	sub	__sp, __sp, #8
	mov	__v4, __a3
	add	__v1, __a1, #4736
	add	__v1, __v1, #20
	add	__a1, __a1, #23040
	add	__a1, __a1, #148
	add	__lr, __a4, __a4, asl #3
	ldr	__a3, [__a1, __a4, asl #2]
	mov	__lr, __lr, asl #9
	add	__ip, __a3, __a3, asl #3
	add	__ip, __v1, __ip, asl #10
	add	__v5, __ip, __lr
	rsb	__a3, __a3, #1
	add	__ip, __a3, __a3, asl #3
	add	__v1, __v1, __ip, asl #10
	ldr	__ip, [__fp, #4]
	mov	__v6, #0
	ldr	__v2, [__ip, #20]
	add	__v3, __v1, __lr
	str	__a3, [__a1, __a4, asl #2]
	cmp	__v2, __v6
	mov	__v2, __a2
	beq	|L..702|
	add	__v6, __v6, #2
	mov	__a1, __v2
	mov	__a2, __v5
	ldr	__a4, |L..726|
	mov	__a3, __v3
	str	__v4, [__sp, #0]
	bl	|dct36|
	add	__a1, __v2, #144
	add	__a2, __v5, #144
	add	__a3, __v3, #144
	add	__v5, __v5, #288
	add	__v3, __v3, #288
	add	__ip, __v4, #8
	ldr	__a4, |L..726|+4
	add	__v4, __v4, #16
	str	__ip, [__sp, #0]
	bl	|dct36|
|L..702|
	ldr	__lr, [__fp, #4]
	ldr	__a3, [__lr, #16]
	cmp	__a3, #2
	bne	|L..703|
	ldr	__ip, [__lr, #64]
	cmp	__v6, __ip
	bge	|L..709|
|L..707|
	add	__v1, __v6, __v6, asl #3
	mov	__v1, __v1, asl #4
	add	__a1, __v2, __v1
	mov	__a2, __v5
	mov	__a3, __v3
	ldr	__a4, |L..726|+8
	add	__v6, __v6, #2
	str	__v4, [__sp, #0]
	bl	|dct12|
	add	__v1, __v1, #144
	add	__a1, __v2, __v1
	add	__a2, __v5, #144
	add	__a3, __v3, #144
	add	__ip, __v4, #8
	ldr	__a4, |L..726|+12
	add	__v4, __v4, #16
	str	__ip, [__sp, #0]
	bl	|dct12|
	ldr	__a1, [__fp, #4]
	add	__v5, __v5, #288
	ldr	__ip, [__a1, #64]
	add	__v3, __v3, #288
	cmp	__v6, __ip
	blt	|L..707|
	b	|L..709|
|L..703|
	ldr	__a2, [__fp, #4]
	ldr	__ip, [__a2, #64]
	cmp	__v6, __ip
	bge	|L..709|
	add	__ip, __a3, __a3, asl #3
	mov	__ip, __ip, asl #5
	str	__ip, [__sp, #4]
|L..713|
	add	__v1, __v6, __v6, asl #3
	mov	__v1, __v1, asl #4
	add	__a1, __v2, __v1
	ldr	__ip, [__sp, #4]
	mov	__a2, __v5
	ldr	__lr, |L..726|
	mov	__a3, __v3
	str	__v4, [__sp, #0]
	add	__a4, __ip, __lr
	bl	|dct36|
	add	__v1, __v1, #144
	add	__a1, __v2, __v1
	ldr	__ip, [__sp, #4]
	add	__a2, __v5, #144
	ldr	__lr, |L..726|+4
	add	__a3, __v3, #144
	add	__a4, __ip, __lr
	add	__ip, __v4, #8
	str	__ip, [__sp, #0]
	bl	|dct36|
	add	__v6, __v6, #2
	add	__v4, __v4, #16
	ldr	__a1, [__fp, #4]
	add	__v5, __v5, #288
	ldr	__ip, [__a1, #64]
	add	__v3, __v3, #288
	cmp	__v6, __ip
	blt	|L..713|
|L..709|
	cmp	__v6, #31
	bgt	|L..725|
	adr	__v1, |L..726|+16
	ldmia	__v1, {__v1-__v2}
|L..718|
	mov	__a3, #0
	add	__lr, __v4, #8
	add	__a4, __v6, #1
|L..722|
	ldmia	__v5!, {__a1-__a2}
	add	__ip, __v4, __a3, asl #8
	stmia	__ip, {__a1-__a2}
	add	__a3, __a3, #1
	cmp	__a3, #17
	stmia	__v3!, {__v1-__v2}
	ble	|L..722|
	mov	__v6, __a4
	mov	__v4, __lr
	cmp	__v6, #31
	ble	|L..718|
|L..725|
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..727|
	ALIGN
|L..726|
	DCD	|win|
	DCD	|win1|
	DCD	|win|+576
	DCD	|win1|+576
	DCD &0, &0	; double 0.00000000000000000000e0
	ALIGN
	EXPORT	|do_layer3_sideinfo|
|do_layer3_sideinfo|
	; args = 0, pretend = 0, frame = 4, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	bllt	|__rt_stkovf_split_small|
	sub	__sp, __sp, #4
	ldr	__lr, [__a1, #8]
	ldr	__v2, [__a1, #0]
	ldr	__ip, [__a1, #48]
	ldr	__a4, [__a1, #36]
	cmp	__v2, #1
	moveq	__lr, #0
	cmp	__ip, #1
	bne	|L..730|
	ldr	__ip, [__a1, #52]
	and	__a3, __ip, #2
	b	|L..731|
|L..730|
	mov	__a3, #0
|L..731|
	ldr	__ip, [__a1, #12]
	cmp	__ip, #0
	beq	|L..732|
	mov	__v3, #1
	ldr	__v1, |L..745|
	mov	__a2, __v2
	str	__lr, [__sp, #0]
	mov	__a1, __v1
	bl	|III_get_side_info_2|
	b	|L..744|
|L..732|
	mov	__v3, #2
	mov	__a2, __v2
	ldr	__v1, |L..745|
	str	__lr, [__sp, #0]
	mov	__a1, __v1
	bl	|III_get_side_info_1|
|L..744|
	mov	__v4, __v1
	mov	__lr, #0
	mov	__a3, __lr
	cmp	__lr, __v3
	bge	|L..735|
	ldr	__v1, |L..745|+4
|L..737|
	mov	__a4, #0
	cmp	__a4, __v2
	add	__a1, __a3, #1
	bge	|L..736|
	add	__ip, __a3, __a3, asl #1
	add	__ip, __a3, __ip, asl #2
	add	__a2, __v1, __ip, asl #3
|L..741|
	add	__ip, __a4, __a4, asl #1
	add	__ip, __a4, __ip, asl #2
	add	__a4, __a4, #1
	add	__ip, __a2, __ip, asl #4
	ldr	__a3, [__ip, #4]
	cmp	__a4, __v2
	add	__lr, __lr, __a3
	blt	|L..741|
|L..736|
	mov	__a3, __a1
	cmp	__a3, __v3
	blt	|L..737|
|L..735|
	ldr	__a1, [__v4, #0]
	sub	__a1, __lr, __a1, asl #3
	ldmea	__fp, {__v1, __v2, __v3, __v4, __fp, __sp, __pc}
|L..746|
	ALIGN
|L..745|
	DCD	|sideinfo|
	DCD	|sideinfo|+8
	AREA |C$$zidata1|,NOINIT
|hybridIn.46|
	% 9216	; size=9216
|hybridOut.47|
	% 9216	; size=9216
	AREA |C$$code3|, CODE, READONLY
	ALIGN
	EXPORT	|do_layer3|
|do_layer3|
	; args = 0, pretend = 0, frame = 436, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	sub	__ip, __sp, #436
	cmp	__ip, __sl
	bllt	|__rt_stkovf_split_big|
	sub	__sp, __sp, #436
	str	__a1, [__sp, #324]
	add	__a4, __a1, #60
	str	__a4, [__sp, #348]
	ldr	__v1, [__a4, #8]
	mov	__v2, #0
	str	__v2, [__sp, #344]
	str	__a2, [__sp, #328]
	str	__v1, [__sp, #356]
	ldr	__v1, |L..827|
	ldr	__a2, [__v1, #0]
	ldr	__ip, [__a1, #60]
	str	__a3, [__sp, #332]
	str	__ip, [__sp, #352]
	ldr	__a3, [__a4, #36]
	str	__a3, [__sp, #368]
	bl	|set_pointer|
	cmn	__a1, #1
	bne	|L..748|
|L..824|
	ldr	__a1, [__sp, #344]
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..748|
	ldr	__a4, [__sp, #352]
	cmp	__a4, #1
	bne	|L..749|
	ldr	__v1, [__sp, #344]
	str	__a4, [__sp, #372]
	str	__v1, [__sp, #356]
	b	|L..750|
|L..749|
	ldr	__v2, [__sp, #356]
	cmp	__v2, #0
	movlt	__v2, #2
	movge	__v2, #1
	str	__v2, [__sp, #372]
|L..750|
	ldr	__a3, [__sp, #348]
	ldr	__ip, [__a3, #48]
	cmp	__ip, #1
	bne	|L..753|
	ldr	__ip, [__a3, #52]
	and	__a4, __ip, #2
	str	__a4, [__sp, #360]
	and	__ip, __ip, #1
	str	__ip, [__sp, #364]
	b	|L..754|
|L..753|
	mov	__v1, #0
	str	__v1, [__sp, #364]
	str	__v1, [__sp, #360]
|L..754|
	ldr	__v2, [__sp, #348]
	ldr	__ip, [__v2, #12]
	mov	__a3, #0
	str	__a3, [__sp, #336]
	cmp	__ip, __a3
	moveq	__ip, #2
	movne	__ip, #1
	cmp	__a3, __ip
	str	__ip, [__sp, #376]
	bge	|L..758|
|L..760|
	ldr	__a4, [__sp, #348]
	ldr	__v1, [__sp, #336]
	ldr	__v2, |L..827|+4
	ldr	__ip, [__a4, #12]
	mov	__a3, __v1, asl #1
	str	__a3, [__sp, #424]
	cmp	__ip, #0
	add	__ip, __a3, __v1
	add	__ip, __v1, __ip, asl #2
	add	__v1, __v2, __ip, asl #3
	beq	|L..761|
	add	__a1, __sp, #8
	mov	__a2, __v1
	mov	__a3, #0
	bl	|III_get_scale_factors_2|
	b	|L..825|
|L..761|
	add	__a1, __sp, #8
	mov	__a2, __v1
	bl	|III_get_scale_factors_1|
|L..825|
	mov	__ip, __a1
	ldr	__a1, |L..827|+8
	add	__a2, __sp, #8
	ldr	__a4, [__sp, #368]
	mov	__a3, __v1
	str	__ip, [__sp, #0]
	bl	|III_dequantize_sample|
	cmp	__a1, #0
	bne	|L..824|
	ldr	__ip, [__sp, #352]
	cmp	__ip, #2
	bne	|L..764|
	ldr	__a3, [__sp, #348]
	ldr	__a4, [__sp, #424]
	ldr	__v1, [__sp, #336]
	ldr	__ip, [__a3, #12]
	add	__a3, __a4, __v1
	cmp	__ip, #0
	ldr	__ip, |L..827|+12
	add	__a3, __v1, __a3, asl #2
	add	__a3, __ip, __a3, asl #3
	str	__a3, [__sp, #380]
	beq	|L..765|
	mov	__a2, __a3
	ldr	__a3, [__sp, #364]
	add	__a1, __sp, #164
	bl	|III_get_scale_factors_2|
	b	|L..826|
|L..765|
	ldr	__a2, [__sp, #380]
	add	__a1, __sp, #164
	bl	|III_get_scale_factors_1|
|L..826|
	mov	__ip, __a1
	ldr	__a3, [__sp, #380]
	ldr	__a1, |L..827|+16
	ldr	__a4, [__sp, #368]
	add	__a2, __sp, #164
	str	__ip, [__sp, #0]
	bl	|III_dequantize_sample|
	cmp	__a1, #0
	bne	|L..824|
	ldr	__v2, [__sp, #360]
	cmp	__v2, #0
	beq	|L..768|
	mov	__v6, __a1
|L..772|
	ldr	__a3, |L..827|+8
	mov	__v3, __v6, asl #3
	ldr	__a4, |L..827|+16
	add	__ip, __v3, __a3
	ldmia	__ip, {__v4-__v5}
	add	__v3, __v3, __a4
	ldmia	__v3, {__v1-__v2}
	add	__v6, __v6, #1
	str	__ip, [__sp, #432]
	mov	__a2, __v5
	mov	__a1, __v4
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__subdf3|
	stmia	__v3, {__a1-__a2}
	mov	__a2, __v5
	mov	__a1, __v4
	mov	__a4, __v2
	mov	__a3, __v1
	bl	|__adddf3|
	ldr	__ip, [__sp, #432]
	cmp	__v6, #576
	stmia	__ip, {__a1-__a2}
	blt	|L..772|
|L..768|
	ldr	__v1, [__sp, #364]
	cmp	__v1, #0
	beq	|L..774|
	ldr	__a1, |L..827|+8
	ldr	__v2, [__sp, #360]
	ldr	__a3, [__sp, #380]
	ldr	__a4, [__sp, #348]
	str	__v2, [__sp, #0]
	ldr	__ip, [__a4, #12]
	ldr	__a4, [__sp, #368]
	add	__a2, __sp, #164
	str	__ip, [__sp, #4]
	bl	|III_i_stereo|
|L..774|
	ldr	__ip, [__sp, #364]
	ldr	__v1, [__sp, #360]
	cmp	__v1, #0
	orrne	__ip, __ip, #1
	cmp	__ip, #0
	bne	|L..776|
	ldr	__v2, [__sp, #356]
	cmp	__v2, #3
	bne	|L..775|
|L..776|
	ldr	__a3, [__sp, #424]
	ldr	__a4, [__sp, #336]
	ldr	__v1, [__sp, #380]
	ldr	__v2, |L..827|
	add	__ip, __a3, __a4
	add	__ip, __a4, __ip, asl #2
	mov	__ip, __ip, asl #3
	ldr	__a4, [__v1, #64]
	add	__a2, __v2, #72
	ldr	__a3, [__a2, __ip]
	cmp	__a4, __a3
	strhi	__a4, [__a2, __ip]
|L..777|
	ldrls	__ip, [__sp, #380]
	strls	__a3, [__ip, #64]
|L..775|
	ldr	__a3, [__sp, #356]
	cmp	__a3, #1
	beq	|L..786|
	cmp	__a3, #3
	bne	|L..764|
	ldr	__v4, |L..827|+8
	ldr	__a4, [__sp, #380]
	mov	__v1, #0
	ldr	__ip, [__a4, #64]
	add	__v5, __v4, #4608
	add	__a2, __ip, __ip, asl #3
	cmp	__v1, __a2, asl #1
	bge	|L..764|
	mov	__v3, __a2
|L..784|
	ldmia	__v4, {__a1-__a2}
	ldmia	__v5!, {__a3-__a4}
	add	__v1, __v1, #1
	bl	|__adddf3|
	cmp	__v1, __v3, asl #1
	stmia	__v4!, {__a1-__a2}
	blt	|L..784|
	b	|L..764|
|L..828|
	ALIGN
|L..827|
	DCD	|sideinfo|
	DCD	|sideinfo|+8
	DCD	|hybridIn.46|
	DCD	|sideinfo|+216
	DCD	|hybridIn.46|+4608
|L..786|
	ldr	__a1, |L..829|
	ldr	__v1, [__sp, #380]
	mov	__a3, #0
	ldr	__ip, [__v1, #64]
	add	__a4, __a1, #4608
	add	__ip, __ip, __ip, asl #3
	mov	__a2, __ip, asl #1
	cmp	__a3, __a2
	bge	|L..764|
|L..790|
	add	__a3, __a3, #1
	ldmia	__a4!, {__v1-__v2}
	cmp	__a3, __a2
	stmia	__a1!, {__v1-__v2}
	blt	|L..790|
|L..764|
	mov	__v2, #0
	str	__v2, [__sp, #340]
	ldr	__ip, [__sp, #372]
	ldr	__a3, [__sp, #336]
	cmp	__v2, __ip
	add	__a3, __a3, #1
	str	__a3, [__sp, #416]
	bge	|L..795|
	ldr	__a4, [__sp, #424]
	ldr	__v1, [__sp, #336]
	ldr	__v2, |L..829|+4
	add	__ip, __a4, __v1
	add	__ip, __v1, __ip, asl #2
	add	__ip, __v2, __ip, asl #3
	str	__ip, [__sp, #388]
|L..797|
	ldr	__a3, [__sp, #340]
	ldr	__a4, [__sp, #388]
	ldr	__v1, [__sp, #340]
	ldr	__v2, |L..829|
	add	__ip, __a3, __a3, asl #1
	add	__ip, __a3, __ip, asl #2
	add	__ip, __a4, __ip, asl #4
	str	__ip, [__sp, #384]
	mov	__a4, __v1, asl #3
	ldr	__a3, [__ip, #16]
	add	__ip, __a4, __v1
	add	__v3, __v2, __ip, asl #9
	str	__a4, [__sp, #428]
	cmp	__a3, #2
	bne	|L..798|
	ldr	__a3, [__sp, #384]
	ldr	__ip, [__a3, #20]
	add	__a4, __v1, #1
	str	__a4, [__sp, #420]
	cmp	__ip, #0
	beq	|L..800|
	mov	__ip, #1
	b	|L..801|
|L..798|
	ldr	__v1, [__sp, #384]
	ldr	__ip, [__v1, #64]
	sub	__ip, __ip, #1
|L..801|
	add	__v3, __v3, #144
	ldr	__v2, [__sp, #340]
	cmp	__ip, #0
	str	__v3, [__sp, #392]
	add	__v2, __v2, #1
	str	__v2, [__sp, #420]
	beq	|L..800|
|L..804|
	ldr	__a3, [__sp, #392]
	mov	__a4, #7
	str	__a4, [__sp, #408]
	ldr	__v1, |L..829|+8
	sub	__ip, __ip, #1
	str	__ip, [__sp, #412]
	ldr	__v2, |L..829|+12
	str	__a3, [__sp, #404]
	str	__v1, [__sp, #396]
	str	__v2, [__sp, #400]
|L..807|
	ldr	__ip, [__sp, #404]
	ldr	__v1, [__sp, #396]
	ldr	__v2, [__sp, #392]
	ldmdb	__ip!, {__v5-__v6}
	str	__ip, [__sp, #404]
	ldmia	__v1, {__a3-__a4}
	mov	__a2, __v6
	mov	__a1, __v5
	ldmia	__v2, {__v3-__v4}
	bl	|__muldf3|
	ldr	__ip, [__sp, #400]
	mov	__v2, __a2
	mov	__v1, __a1
	ldmia	__ip, {__a3-__a4}
	mov	__a2, __v4
	mov	__a1, __v3
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__subdf3|
	ldr	__a3, [__sp, #404]
	stmia	__a3, {__a1-__a2}
	ldr	__v1, [__sp, #396]
	ldmia	__v1!, {__a3-__a4}
	mov	__a2, __v4
	mov	__a1, __v3
	str	__v1, [__sp, #396]
	bl	|__muldf3|
	ldr	__v2, [__sp, #400]
	ldmia	__v2!, {__a3-__a4}
	str	__v2, [__sp, #400]
	mov	__v2, __a2
	mov	__v1, __a1
	mov	__a2, __v6
	mov	__a1, __v5
	bl	|__muldf3|
	mov	__a4, __a2
	mov	__a3, __a1
	mov	__a2, __v2
	mov	__a1, __v1
	bl	|__adddf3|
	ldr	__ip, [__sp, #408]
	ldr	__a3, [__sp, #392]
	subs	__ip, __ip, #1
	str	__ip, [__sp, #408]
	stmia	__a3!, {__a1-__a2}
	str	__a3, [__sp, #392]
	bpl	|L..807|
	ldr	__ip, [__sp, #412]
	add	__a3, __a3, #80
	str	__a3, [__sp, #392]
	cmp	__ip, #0
	bne	|L..804|
|L..800|
	ldr	__a1, [__sp, #324]
	ldr	__a4, [__sp, #428]
	ldr	__v1, [__sp, #340]
	ldr	__v2, |L..829|
	ldr	__ip, |L..829|+16
	add	__a3, __a4, __v1
	mov	__a3, __a3, asl #9
	add	__a2, __a3, __v2
	mov	__a4, __v1
	ldr	__v1, [__sp, #384]
	add	__a3, __a3, __ip
	str	__v1, [__sp, #0]
	bl	|III_hybrid|
	ldr	__v2, [__sp, #420]
	ldr	__ip, [__sp, #372]
	str	__v2, [__sp, #340]
	cmp	__v2, __ip
	blt	|L..797|
|L..795|
	ldr	__v4, |L..829|+16
	mov	__v3, #0
	add	__v5, __v4, #4608
|L..816|
	ldr	__a3, [__sp, #356]
	cmp	__a3, #0
	blt	|L..817|
	ldr	__a1, [__sp, #324]
	ldr	__a4, |L..829|+16
	ldr	__a3, [__sp, #328]
	add	__a2, __a4, __v3, asl #8
	ldr	__a4, [__sp, #332]
	bl	|synth_1to1_mono|
	ldr	__v1, [__sp, #344]
	add	__v1, __v1, __a1
	str	__v1, [__sp, #344]
	b	|L..815|
|L..817|
	ldr	__a1, [__sp, #324]
	add	__ip, __sp, #320
	str	__ip, [__sp, #0]
	ldr	__v2, [__sp, #332]
	mov	__v1, __v3, asl #8
	ldr	__a4, [__sp, #328]
	add	__a2, __v1, __v4
	ldr	__ip, [__v2, #0]
	mov	__a3, #0
	str	__ip, [__sp, #320]
	bl	|synth_1to1|
	ldr	__ip, [__sp, #344]
	ldr	__a4, [__sp, #328]
	add	__a2, __v1, __v5
	str	__v2, [__sp, #0]
	add	__ip, __ip, __a1
	ldr	__a1, [__sp, #324]
	mov	__a3, #1
	str	__ip, [__sp, #344]
	bl	|synth_1to1|
	ldr	__a3, [__sp, #344]
	add	__a3, __a3, __a1
	str	__a3, [__sp, #344]
|L..815|
	add	__v3, __v3, #1
	cmp	__v3, #17
	ble	|L..816|
	ldr	__a4, [__sp, #416]
	ldr	__v1, [__sp, #376]
	str	__a4, [__sp, #336]
	cmp	__a4, __v1
	blt	|L..760|
|L..758|
	ldr	__a1, [__sp, #344]
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..830|
	ALIGN
|L..829|
	DCD	|hybridIn.46|
	DCD	|sideinfo|+8
	DCD	|aa_cs|
	DCD	|aa_ca|
	DCD	|hybridOut.47|
	AREA |C$$zidata2|,NOINIT
|ispow|
	% 65656	; size=65656
|aa_ca|
	% 64	; size=64
|aa_cs|
	% 64	; size=64
|COS1|
	% 576	; size=576
|win|
	% 1152	; size=1152
|win1|
	% 1152	; size=1152
|gainpow2|
	% 3024	; size=3024
|COS9|
	% 72	; size=72
|COS6_1|
	% 8	; size=8
|COS6_2|
	% 8	; size=8
|tfcos36|
	% 72	; size=72
|tfcos12|
	% 24	; size=24
	AREA |Common$$longLimit|, DATA, COMMON
|longLimit|
	% 828	; size=828
	EXPORT	|longLimit|
	AREA |Common$$shortLimit|, DATA, COMMON
|shortLimit|
	% 504	; size=504
	EXPORT	|shortLimit|
	AREA |C$$zidata3|,NOINIT
|mapbuf0|
	% 5472	; size=5472
|mapbuf1|
	% 5616	; size=5616
|mapbuf2|
	% 1584	; size=1584
|map|
	% 108	; size=108
|mapend|
	% 108	; size=108
|n_slen2|
	% 2048	; size=2048
|i_slen2|
	% 1024	; size=1024
|tan1_1|
	% 128	; size=128
|tan2_1|
	% 128	; size=128
|tan1_2|
	% 128	; size=128
|tan2_2|
	% 128	; size=128
|pow1_1|
	% 256	; size=256
|pow2_1|
	% 256	; size=256
|pow1_2|
	% 256	; size=256
|pow2_2|
	% 256	; size=256
	AREA |Common$$sideinfo|, DATA, COMMON
|sideinfo|
	% 424	; size=424
	EXPORT	|sideinfo|
	END
